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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. document no. u18685ej3v0ud00 (3rd edition) date published february 2008 ns printed in japan 2007 pd179f110 pd179f111 pd179f112 pd179f113 pd179f114 pd179f122 pd179f123 pd179f124 pd179f11x, 179f12x microcontrollers 8-bit single-chip microcontrollers user?s manual user?s manual u18685ej3v0ud 2 [memo] user?s manual u18685ej3v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 user?s manual u18685ej3v0ud 4 windows and windows nt are registered trademarks or trademarks of microsoft co rporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. superflash is a registered trademark of silicon stor age technology, inc. in several countries including the united states and japan. user?s manual u18685ej3v0ud 5 caution: this product uses superflash ? technology licensed from silicon storage technology, inc. the information in this document is current as of february, 2008. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec e lectronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": user?s manual u18685ej3v0ud 6 introduction readers this manual is intended for user engineer s who wish to understand the functions of the pd179f11x, 179f12x microcontrollers and design and develop application systems and programs for these devices. the target products are as follows. pd179f11x, 179f12x microcontrollers: pd179f110, 179f111, 17 9f112, 179f113, 179f114, 179f122, 179f123, 179f124 purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the pd179f11x, 179f12x microcontrollers manual is separated into two parts: this manual and the instructions editi on (common to 78k0 microcontrollers). pd179f11x, 179f12x microcontrollers user?s manual (this manual) 78k/0 series user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications ? cpu functions ? instruction set ? explanation of each instruction how to read this manual it is assumed that the readers of this ma nual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? to gain a general understanding of functions: read this manual in the order of the contents . the mark ? user?s manual u18685ej3v0ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representations: (overscore over pin and signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representations: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this pu blication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd179f11x, 179f12x microcontrollers user?s manual this manual 78k/0 series instructions user?s manual u12326e documents related to development tools (software) (user?s manuals) document name document no. operation u17199e language u17198e ra78k0 ver. 3.80 assembler package structured assembly language u17197e operation u17201e cc78k0 ver. 3.70 c compiler language u17200e id78k0-qb ver. 3.00 integrat ed debugger operation u18492e pm+ ver. 6.00 u17178e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. user?s manual u18685ej3v0ud 8 documents related to development tools (hardware) (user?s manuals) document name document no. qb-179f124 in-circuit emulator u18586e qb-mini2 on-chip debug emulator with programming function u18371e documents related to flash memo ry programming (u ser?s manuals) document name document no. pg-fp4 flash memory programmer u15260e pg-fp5 flash memory programme u18865e other documents document name document no. semiconductor selection guide ? products and packages ? x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device m ount manual? website (h ttp://www.necel.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. user?s manual u18685ej3v0ud 9 contents chapter 1 outline ........................................................................................................... ................. 15 1.1 features ................................................................................................................... ................. 15 1.2 applications ............................................................................................................... .............. 15 1.3 ordering information ....................................................................................................... ........ 16 1.4 application circuit........................................................................................................ ............ 16 1.5 pin configuration (top view).................................. ............................................................. ... 17 1.6 pd179f11x, 179f12x microcontrollers lineup ................................................................... 19 1.7 block diagram.............................................................................................................. ............ 19 1.8 outline of functions ....................................................................................................... ......... 20 chapter 2 pin functions .................................................................................................... ........... 22 2.1 pin function list.......................................................................................................... ............ 22 2.2 description of pin functions .................................... ........................................................... ... 24 2.2.1 p00 to p07 (por t 0)..................................................................................................... ......................24 2.2.2 p10 to p17 (por t 1)..................................................................................................... ......................25 2.2.3 p20 to p27 (por t 2)..................................................................................................... ......................25 2.2.4 p30 to p35 (port 3) (38-pin produc ts only) .............................................................................. .........26 2.2.5 p120 to p123 (por t 12).................................................................................................. ...................26 2.2.6 regc .................................................................................................................... ..........................27 2.2.7 v dd .............................................................................................................................. .....................27 2.2.8 v ss ............................................................................................................................... ....................27 2.2.9 flmd0 ................................................................................................................... ..........................27 2.3 pin i/o circuits and recommended connection of unused pins....................................... 27 chapter 3 cpu architecture ................................................................................................. ..... 30 3.1 memory space............................................................................................................... ........... 30 3.1.1 internal progr am memory space ........................................................................................... ...........37 3.1.2 internal dat a memory space .............................................................................................. ..............38 3.1.3 special function register (sfr) area .................................................................................... ............38 3.1.4 data me mory addr essing.................................................................................................. ...............38 3.2 processor registers ........................................................................................................ ........ 44 3.2.1 contro l regist ers....................................................................................................... ........................44 3.2.2 general-pur pose registers ............................................................................................... ................48 3.2.3 special functi on register s (sfrs)....................................................................................... ..............49 3.3 instruction address addressing .................................. .......................................................... 5 3 3.3.1 relati ve addre ssing ..................................................................................................... ....................53 3.3.2 immedi ate addres sing.................................................................................................... ..................54 3.3.3 table indi rect addr essing............................................................................................... ..................55 3.3.4 regist er addre ssing ..................................................................................................... ....................55 3.4 operand address addressi ng ................................................................................................ 5 6 3.4.1 impli ed addre ssing...................................................................................................... .....................56 3.4.2 regist er addre ssing ..................................................................................................... ....................57 3.4.3 direct addre ssing ....................................................................................................... ......................58 user?s manual u18685ej3v0ud 10 3.4.4 short di rect addr essing ................................................................................................. .................. 59 3.4.5 special function register (sfr ) addres sing .............................................................................. ....... 60 3.4.6 register i ndirect addr essi ng............................................................................................ ................ 61 3.4.7 based addre ssing ........................................................................................................ ................... 62 3.4.8 based in dexed addr essing................................................................................................ .............. 63 3.4.9 stack addre ssing........................................................................................................ ..................... 64 chapter 4 port functions ................................................................................................... ........ 65 4.1 port functions ............................................................................................................. ............. 65 4.2 port configurat ion ......................................................................................................... .......... 67 4.2.1 po rt 0 .................................................................................................................. ............................ 68 4.2.2 po rt 1 .................................................................................................................. ............................ 73 4.2.3 po rt 2 .................................................................................................................. ............................ 74 4.2.4 port 3 (38- pin produc ts only) ........................................................................................... ................ 77 4.2.5 po rt 12 ................................................................................................................. ........................... 78 4.3 registers controlling port functi on ...................................................................................... 81 4.4 port function operations................................................. .................................................. ..... 85 4.4.1 writi ng to i/o port ..................................................................................................... ....................... 85 4.4.2 reading from i/o port................................................................................................... ................... 85 4.4.3 operatio ns on i/o port.................................................................................................. ................... 85 4.5 settings of port mode register, output latc h, pull-up resistor op tion register, and port output mode register when using alternate functi on....................................................... 86 4.6 cautions on 1-bit manipulation in struction for port register n (p n) .................................. 87 chapter 5 clock generator .................................................................................................. .... 88 5.1 functions of clock generator....................................... ........................................................ .. 88 5.2 configuration of clock genera tor .......................................................................................... 8 9 5.3 registers controlling clock generator ....................... .......................................................... 91 5.4 system clock oscillator .................................................................................................... ...... 99 5.4.1 x1 oscill ator........................................................................................................... .......................... 99 5.4.2 internal hi gh-speed os cillator .......................................................................................... ...............100 5.4.3 internal lo w-speed os cillator........................................................................................... ................100 5.4.4 pr escaler............................................................................................................... .........................101 5.5 clock generator operation .............................................. .................................................... . 101 5.6 controlling clock .......................................................................................................... ......... 103 5.6.1 example of controlli ng high-speed syst em clock.......................................................................... ..103 5.6.2 example of controlling intern al high-speed osc illation clock...........................................................1 05 5.6.3 example of controlling intern al low-speed osci llation clock ............................................................1 07 5.6.4 clocks supplied to cp u and periphera l hardw are.......................................................................... 108 5.6.5 cpu clock stat us transiti on diagr am ..................................................................................... .........109 5.6.6 condition before changing cpu clock and processi ng after changing cpu cl ock .........................112 5.6.7 time required for switchover of cpu clock and main system cl ock ...............................................112 5.6.8 conditions before clock osc illation is stopp ed .......................................................................... ......113 5.6.9 peripher al hardware and source clocks ................................................................................... ......114 user?s manual u18685ej3v0ud 11 chapter 6 16-bit timer/event counter 00........................................................................... 115 6.1 functions of 16-bit timer/ event counter 00 .............................. ......................................... 115 6.2 configuration of 16-bit timer/e vent counter 00................................................................. 116 6.3 registers controlling 16-bit ti mer/event counter 00 ..................... ................................... 121 6.4 operation of 16-bit timer/event counter 00 ....................................................................... 129 6.4.1 interval timer oper ation ................................................................................................ ..................129 6.4.2 square wave output op eration ............................................................................................ ...........132 6.4.3 external event counter operatio n ........................................................................................ ...........135 6.4.4 operation in clear & start mode entered by ti 000 pin valid ed ge input..........................................138 6.4.5 free-runni ng timer oper ation ............................................................................................ .............151 6.4.6 ppg out put operat ion .................................................................................................... ................160 6.4.7 one-shot pul se output operatio n......................................................................................... ...........163 6.4.8 pulse width m easurement operatio n....................................................................................... .......168 6.5 special use of tm00 ........................................................................................................ ...... 176 6.5.1 rewriting cr010 during tm00 operatio n................................................................................... ....176 6.5.2 setting l vs00 and lvr00 ................................................................................................. ............176 6.6 cautions for 16-bit timer/event counter 00........................................................................ 178 chapter 7 8-bit timer/event counters 50 and 51 .......................................................... 182 7.1 functions of 8-bit time r/event counters 50 and 51.................. ......................................... 182 7.2 configuration of 8-bit timer/event counters 50 a nd 51 .................................................... 182 7.3 registers controlling 8- bit timer/event counters 50 and 51............................................ 185 7.4 operations of 8-bit timer/event counters 50 and 51......................................................... 190 7.4.1 operation as interval timer............................................................................................. ................190 7.4.2 operation as ex ternal event count er ..................................................................................... .........192 7.4.3 square-wave output op eration ............................................................................................ ...........193 7.4.4 pwm out put operat ion .................................................................................................... ...............194 7.5 cautions for 8-bit timer/event counters 50 and 51 ........................................................... 198 chapter 8 8-bit timers h0 and h1 ........................................................................................ .. 199 8.1 functions of 8-bit timers h0 and h1 ................................................................................... 199 8.2 configuration of 8-bit timers h0 and h1............................................................................. 199 8.3 registers controlling 8-bi t timers h0 and h1 .................................................................... 203 8.4 operation of 8-bit timers h0 and h1 ..................... .............................................................. 208 8.4.1 operation as interv al timer/squar e-wave output .......................................................................... ..208 8.4.2 operatio n as pw m out put................................................................................................. .............211 8.4.3 carrier generator operat ion (8-bit ti mer h1 only) ....................................................................... ....217 chapter 9 watchdog timer ................................................................................................... .... 224 9.1 functions of watchdog timer ...................................... ........................................................ 22 4 9.2 configuration of watchdog timer............................ ............................................................ 225 9.3 register controlling watchdog time r ................................................................................. 226 9.4 operation of watchdog timer .............................................................................................. 22 7 9.4.1 controlling operat ion of watc hdog timer................................................................................. ........227 9.4.2 setting overflow ti me of watc hdog ti mer ................................................................................. .......228 9.4.3 setting window open pe riod of watc hdog ti mer............................................................................ ..229 user?s manual u18685ej3v0ud 12 chapter 10 serial interface uart6 ...................................................................................... 231 10.1 functions of serial interface uart6............................ ........................................................ 231 10.2 configuration of serial interf ace uart6 ............................................................................. 232 10.3 registers controlling serial in terface uart6..................................................................... 235 10.4 operation of serial interface uart6.......................... .......................................................... 243 10.4.1 operat ion stop mode.................................................................................................... ................243 10.4.2 asynchronous serial interface (u art) mode .............................................................................. .244 10.4.3 dedicated ba ud rate g enerat or.......................................................................................... ...........255 10.4.4 calculation of baud rate ....................................................................................................... ........257 chapter 11 interrupt functions ............................................................................................ 2 62 11.1 interrupt function types.................................................................................................. ..... 262 11.2 interrupt sources and configuration ........................... ........................................................ 262 11.3 registers controlling interrupt functions .......................................................................... 266 11.4 interrupt servicing operations ............................................................................................ . 273 11.4.1 maskable interr upt acknow ledgment...................................................................................... ......273 11.4.2 software interrupt request ack nowledg ment .............................................................................. ..275 11.4.3 multiple in terrupt se rvicing ........................................................................................... ................276 11.4.4 interrupt request hold ................................................................................................. ..................279 chapter 12 key interrupt function ..................................................................................... 280 12.1 functions of key interrupt ............................................ .................................................... .... 280 12.2 configuration of key interrupt............................................................................................ .. 280 12.3 register controlling key interrupt ............................. .......................................................... 2 81 chapter 13 standby function ................................................................................................ .. 283 13.1 standby function and configurat ion................................................................................... 283 13.1.1 standby func tion ....................................................................................................... ...................283 13.1.2 registers contro lling standby function................................................................................. .........283 13.2 standby function operation................................................................................................ . 286 13.2.1 ha lt m ode .............................................................................................................. ....................286 13.2.2 st op m ode .............................................................................................................. ...................288 chapter 14 reset function.................................................................................................. ...... 294 14.1 register for confirming reset source................................................................................. 300 chapter 15 power-on-clear circuit...................................................................................... 301 15.1 functions of power-on-c lear circuit ................................................................................... 301 15.2 configuration of power-on-clear circuit ............................................................................. 302 15.3 operation of power-on-clear circuit.......................... .......................................................... 302 15.4 cautions for power-on-clear circuit .................................................................................... 304 chapter 16 low-voltage detector ....................................................................................... 306 16.1 functions of low-voltage detect or...................................................................................... 306 16.2 configuration of low-voltage detector ............................................................................... 307 user?s manual u18685ej3v0ud 13 16.3 registers controlling low-voltage detector ...................................................................... 307 16.4 operation of low-voltage detector ......................... ............................................................ 310 16.4.1 when us ed as re set ..................................................................................................... ................311 16.4.2 when used as interrupt................................................................................................. ...............315 16.5 cautions for low-voltage detector.......................... ............................................................ 319 16.6 ram data retention detector................................... ............................................................ 322 chapter 17 option byte..................................................................................................... .......... 323 17.1 functions of option byte s ................................................................................................. ... 323 17.2 format of option byte ..................................................................................................... ...... 324 chapter 18 flash memory.................................................................................................... ...... 326 18.1 internal memory size switching register ............. .............................................................. 326 18.2 writing with flash memory programmer............... .............................................................. 327 18.3 programming environment................................................................................................... 329 18.4 communication mode ........................................................................................................ ... 329 18.5 handling of pins on board................................................................................................. ... 330 18.5.1 fl md0 pin .............................................................................................................. .....................330 18.5.2 serial interfac e pins .................................................................................................. ...................331 18.5.3 r eset pin .............................................................................................................. .....................332 18.5.4 po rt pins.............................................................................................................. .........................333 18.5.5 re gc pin............................................................................................................... ......................333 18.5.6 other signal pins ...................................................................................................... ....................333 18.5.7 powe r suppl y ........................................................................................................... ....................333 18.6 programming method........................................................................................................ .... 334 18.6.1 controlli ng flash memory ............................................................................................... ..............334 18.6.2 flash memory programmi ng mode .......................................................................................... ....334 18.6.3 selecting communicati on mode ........................................................................................... ........335 18.6.4 communi cation co mmands ................................................................................................. ........335 18.7 security settings......................................................................................................... ........... 336 18.8 flash memory programming by self-programming.. ......................................................... 339 chapter 19 on-chip debug function ..................................................................................... 342 19.1 connecting qb-mini2 ....................................................................................................... ..... 342 19.2 reserved area used by qb-mini2 ....................................................................................... 344 chapter 20 instruction set ................................................................................................. ..... 345 20.1 conventions used in operation list...................... .............................................................. 345 20.1.1 operand identifiers and specificat ion me thods .......................................................................... ..345 20.1.2 description of operation column ........................................................................................ ..........346 20.1.3 description of flag operati on colu mn................................................................................... .........346 20.2 operation list............................................................................................................ ............. 347 20.3 instructions listed by addressing type ............... .............................................................. 355 chapter 21 electrical specifications................................................................................. 358 user?s manual u18685ej3v0ud 14 chapter 22 package drawings ................................................................................................ 369 appendix a development tools............................................................................................... 371 a.1 software package ........................................................................................................... ....... 374 a.2 language processing so ftware............................................................................................ 374 a.3 control software ........................................................................................................... ......... 375 a.4 flash memory writing tools ................................................................................................. 376 a.4.1 when using flash memory programme r pg-fp4, fl-pr4, pg -fp5 and fl -pr5 .........................376 a.4.2 when using on-chip debug emulator with programm ing function qb-mini2 .................................376 a.5 debugging tools (hardware) ................................................................................................ 3 77 a.5.1 when using in-circu it emulator qb-179 f124 ............................................................................... ..377 a.5.2 when using on-chip debug emulator with programm ing function qb-mini2 .................................378 a.6 debugging tools (software) ................................................................................................. 378 appendix b revision history ................................................................................................. ..... 379 b.1 major revisions in this edition............................................................................................ 379 b.2 revision history up to previous editions ................. .......................................................... 381 user?s manual u18685ej3v0ud 15 chapter 1 outline 1.1 features { high speed (1 s: v dd = 1.8 to 3.6 v, high-speed system clock: @ f xh = 2 or 4 mhz operation, 0.5 s: v dd = 2.0 to 3.6 v, high-speed system clock: @ f xh = 4 mhz operation) { general-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks) { rom, ram capacities data memory item part number program memory (rom) internal high-speed ram note pd179f110 4 kb pd179f111 8 kb 512 bytes pd179f112, 179f122 16 kb 768 bytes pd179f113, 179f123 24 kb pd179f114, 179f124 flash memory note 32 kb 1 kb note the internal flash memory, and internal high-speed ram capacities can be changed using the internal memory size switching register (ims). for ims, see 18.1 internal memory size switching register . { on-chip single-power-supply flash memory { self-programming (with boot swap function) { on-chip debug function { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { on-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock) { on-chip key interrupt function { i/o ports: 30-pin products ( pd179f11x microcontrollers) : 26 (n-ch open drain/cmos: 24, p-ch open drain note1 /cmos: 1) 38-pin products ( pd179f12x microcontrollers) : 34 (n-ch open drain: 32, p-ch open drain note1 /cmos: 1) { timer: 6 channels ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 2 channels ? 8-bit timer: 2 channels ? watchdog timer: 1 channel { serial interface: 1 channel ? uart: 1 channel { power supply voltage: v dd = 1.8 to 3.6 v note2 { operating ambient temperature: t a = ?40 to +85 c notes 1. available for a remote control output 2. use this product in a voltage range of 1. 9 to 3.6 v because the detection voltage (v poc ) of the power-on-clear (poc) circuit is 1.8 v 0.1 v. 1.2 applications { preset remote control chapter 1 outline user?s manual u18685ej3v0ud 16 1.3 ordering information ? flash memory version part number package quality grade pd179f110mc-cab-ax 30-pin plastic ssop (7.62 mm (300)) standard pd179f111mc-cab-ax 30-pin plastic ssop (7.62 mm (300)) standard pd179f112mc-cab-ax 30-pin plastic ssop (7.62 mm (300)) standard pd179f113mc-cab-ax 30-pin plastic ssop (7.62 mm (300)) standard pd179f114mc-cab-ax 30-pin plastic ssop (7.62 mm (300)) standard pd179f122mc-gaa-ax 38-pin plastic ssop (7.62 mm (300)) standard pd179f123mc-gaa-ax 38-pin plastic ssop (7.62 mm (300)) standard pd179f124mc-gaa-ax 38-pin plastic ssop (7.62 mm (300)) standard remark products with -ax at the end of the part number are lead-free products. 1.4 application circuit the following figure shows an example of the key matrix : 9 x 10 = 90 keys. by using p04 to p06 and p120, the maximum of 126 keys can be configured (in the case of pd179f11x microcontrollers). 100 k ? 0.47 f p06 4 mhz 3 v chapter 1 outline user?s manual u18685ej3v0ud 17 1.5 pin configuration (top view) ? 30-pin plastic ssop (7.62 mm (300)) p25 p26 p27/intp4 p04/intp3/ocd1a p05/intp2/ocd1b p06/ti50/to50/intp1 p120/exlvi/intp0 v dd p07/rem/toh1 p121/x1/ocd0a p122/x2/exclk/ocd0b v ss regc flmd0 reset/p123/kr8/intp5 28 27 26 30 29 25 24 23 22 21 20 19 18 16 p22 p21 p20 p03/ti010/to00/r x d6 p02/ti000/t x d6 p01/toh0 p00/ti51/to51 p17/kr7 p16/kr6 p14/kr4 p15/kr5 p13/kr3 p12/kr2 p11/kr1 p10/kr0 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 caution connect the regc pin to v ss via a capacitor (0.47 f: recommended). pin identification exclk: external clock input (main system clock) to00, to50, to51, toh0, toh1: timer output exlvi: external potential input txd6: transmit data for low-voltage detector v dd : power supply flmd0: flash programming mode v ss : ground intp0 to intp5: external interrupt input x1, x2: crystal oscillator kr0 to kr8: key return (main system clock) ocd0a, ocd0b, ocd1a, ocd1b: on chip debug input/output p00-p07: port 0 p10-p17: port 1 p20 to p22, p25 to p27: port 2 p120 to p123: port 12 regc: regulator capacitance rem: remote control output reset: reset rxd6: receive data ti000, ti010, ti50, ti51: timer input chapter 1 outline user?s manual u18685ej3v0ud 18 ? 38-pin plastic ssop (7.62 mm (300)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 p25 p26 p27/intp4 p04/intp3/ocd1a p05/intp2/ocd1b p06/ti50/to50/intp1 p120/exlvi/intp0 v dd p07/rem/toh1 p121/x1/ocd0a p122/x2/exclk/ocd0b v ss regc flmd0 reset/p123/kr8/intp5 p22 p21 p20 p03/ti010/to00/r x d6 p02/ti000/t x d6 p01/toh0 p00/ti51/to51 p17/kr7 p16/kr6 p14/kr4 p15/kr5 p13/kr3 p12/kr2 p11/kr1 p10/kr0 p35/kr14 p34/kr13 p33/kr12 p23 p24 p30/kr9 p31/kr10 p32/kr11 caution connect the regc pin to v ss via a capacitor (0.47 f: recommended). pin identification exclk: external clock input (main system clock) to00, to50, to51, toh0, toh1: timer output exlvi: external potential input txd6: transmit data for low-voltage detector v dd : power supply flmd0: flash programming mode v ss : ground intp0 to intp5: external interrupt input x1, x2: crystal oscillator kr0 to kr14: key return (main system clock) ocd0a, ocd0b, ocd1a, ocd1b: on chip debug input/output p00 to p07: port 0 p10 to p17: port 1 p20 to p27: port 2 p120 to p123: port 12 regc: regulator capacitance rem: remote control output reset: reset rxd6: receive data ti000, ti010, ti50, ti51: timer input chapter 1 outline user?s manual u18685ej3v0ud 19 1.6 pd179f11x, 179f12x microcontrollers lineup rom ram 30 pins 38 pins 32 kb pd179f114 pd179f114 24 kb 1 kb pd179f113 pd179f113 16 kb 768 b pd179f112 pd179f112 8 kb pd179f111 ? 4 kb 512 b pd179f110 ? 1.7 block diagram port 0 p00 to p07 8 port 1 p10 to p17 port 2 p20 to p22, p25 to p27 6 port 3 note p30 to p35 note 6 v ss flmd0 v dd 8 power-on-clear/ low-voltage indicator poc/lvi control reset control port 12 key return 8 kr0/p10 to kr7/p17 exlvi/p120 interrupt control intp4/p27 intp5/p123 internal high-speed ram 78k/0 cpu core flash memory 8-bit timer h0 toh0/p01 8-bit timer h1 rem/toh1/p07 ti50/to50/p06 8-bit timer/ event counter 50 watchdog timer rxd6/p03 txd6/p02 serial interface uart6 ti51/to51/p00 8-bit timer/ event counter 51 16-bit timer/ event counter 00 to00/ti010/p03 ti000/p02 internal low-speed oscillator intp2/p05 intp3/p04 intp0/p120 intp1/p06 p23, p24 note 2 6 kr9/p30 to kr14/p35 note kr8/p123 p120 to p122 3 p123 system control reset/p123 x1/p121 x2/exclk/p122 on-chip debug internal high-speed oscillator voltage regulator regc ocd0a/p121 ocd0b/p122 ocd1a/p04 ocd1a/p05 note 38-pin products only chapter 1 outline user?s manual u18685ej3v0ud 20 1.8 outline of functions item pd179f110 pd179f111 pd179f112 pd179f113 pd179f114 pd179f122 pd179f123 pd179f124 flash memory (self-programming supported) note 4 k 8 k 16 k 24 k 32k 16 k 24 k 32k internal memory (bytes) high-speed ram note 512 768 1 k 768 1 k memory space 64 kb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 4 mhz: v dd = 1.8 to 3.6 v main system clock (oscillation frequency) internal high- speed oscillation clock internal oscillation 4 mhz 2%: v dd = 1.8 to 3.6 v internal low-speed oscillation clock (for wdt) internal oscillation 240 khz (typ.): v dd = 1.8 to 3.6 v general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 1 s (v dd = 1.8 to 3.6 v, high-speed system clock: @ f xh = 2 or 4 mhz operation) 0.5 s (v dd = 2.0 to 3.6 v, high-speed system clock: @ f xh = 4 mhz operation) instruction set 8-/16-bit operation multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulate (set, reset, test, and boolean operation) bcd adjust, etc. i/o ports total: 26 (30-pin produ cts) 34 (38-pin products) n-ch open-drain output/cmos i/o: 24 32 p-ch open-drain output/cmos i/o: 1 1 cmos input: 1 1 timers 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels 8-bit timer: 2 channels watchdog timer: 1 channel timer outputs 5 (pwm output: 2, carrier generator output for remote control: 1) serial interface uart mode: 1 channel internal 10 vectored interrupt sources external 8 key interrupt key interrupt occurs by detecting falling edge of key input pins (kr0 and kr8). key interrupt occurs by detecting falling edge of key input pins (kr0 to kr14). reset reset using reset pin internal reset by watchdog timer internal reset by power-on-clear internal reset by low-voltage detector on-chip debug function provided power supply voltage v dd = 1.8 to 3.6 v operating ambient temperature t a = ?40 to +85 c package 30-pin plastic ssop (7.62 mm (300)) 38-pin plastic ssop (7.62 mm (300)) note the internal flash memory capacity and internal high-speed ram capacity can be changed using the internal memory size switching register (ims). chapter 1 outline user?s manual u18685ej3v0ud 21 an outline of the timer is shown below. 16-bit timer/ event counter 00 8-bit timer/ event counters 50 and 51 8-bit timers h0 and h1 tm00 tm50 tm51 tmh0 tmh1 watchdog timer interval timer 1 channel 1 channel 1 channel 1 channel 1 channel ? external event counter 1 channel 1 channel 1 channel ? ? ? pwm output ? ? ? 1 output 1 output ? pulse width measurement 2 inputs ? ? ? ? ? square-wave output 1 output 1 output 1 output ? ? ? carrier generator ? ? note ? 1 output note ? function watchdog timer ? ? ? ? ? 1 channel interrupt source 2 1 1 1 1 ? note tm51 and tmh1 can be used in combination as a carrier generator mode. user?s manual u18685ej3v0ud 22 chapter 2 pin functions 2.1 pin function list (1) port functions function name i/o function after reset alternate function p00 ti51/to51 p01 toh0 p02 ti000/txd6 p03 ti010/to00/ r x d6 p04 intp3/ocd1a p05 intp2/ocd1b p06 ti50/to50/intp1 p07 i/o port 0. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified in 1-bit units. p00 to p06 can be set to n-ch open-drain output or cmos i/o in 1-bit units. p07 can be set to p-ch open-drain output or cmos i/o in 1-bit units. this pin can be used as a carrier generator output for remote control by specifying p-ch open-drain output. input port rem/toh1 p10 to p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified in 1-bit units. p10 to p17 can be set to n-ch open-drain output or cmos i/o in 1-bit units. input port kr0 to kr7 p20 to p22 ? p23 note , p24 note ? p25, p26 ? p27 i/o port 2. 38-pin products: 8-bit i/o port 30-pin products: 6-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified in 1-bit units. p20 to p22, p23 note , p24 note , p25 to p27 can be set to n-ch open-drain output or cmos i/o in 1-bit units. input port intp4 p30 to p35 note i/o port 3 note . 6-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified in 1-bit units. p30 to p35 can be set to n-ch open-drain output or cmos i/o in 1-bit units. input port kr9 to kr14 note p120 exlvi/intp0 p121 x1/ocd0a p122 i/o x2/exclk/ocd0b p123 input port 12. 3-bit i/o port and 1-bit input-only port. input/output can be specified in 1-bit units in p120 to p122. use of an on-chip pull-up resistor can be specified in only p120 and p123. p120 to p122 can be set to n- ch open-drain output or cmos i/o in 1-bit units. input port reset/kr8/ intp5 note 38-pin products only chapter 2 pin functions user?s manual u18685ej3v0ud 23 (2) non-port functions (1/2) function name i/o function after reset alternate function exlvi input potential input for external low-voltage detection input port p120/intp0 flmd0 ? flash memory programming mode setting ? ? intp0 p120/exlvi intp1 p06/ti50/to50 intp2 p05/ocd1b intp3 p04/ocd1a intp4 p27 intp5 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p123/reset/ kr8 kr0 to kr7 p10-p17 kr8 p123/reset/ intp5 kr9 to kr15 note input key interrupt input input port p30 to p35 note regc ? connecting regulator output stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 f: recommended). ? ? rem output remote control output input port p07/toh1 reset input system reset input input port p123/kr8/intp5 rxd6 input serial data input to asynchronous serial interface input port p03/ti010/to00 ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 p02/txd6 ti010 input capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 input port p03/to00/r x d6 ti50 external count clock input to 8-bi t timer/event counter 50 p06/to50/intp1 ti51 input external count clock input to 8-bit timer/event counter 51 input port p00/to51 to00 output 16-bit timer/event counter 00 output input port p03/ti010/rxd6 to50 8-bit timer/event counter 50 output p06/ti50/intp1 to51 output 8-bit timer/event counter 51 output input port p00/ti51 toh0 8-bit timer h0 output p01 toh1 output 8-bit timer h1 output input port p07/rem txd6 output serial data output from asynch ronous serial interface input port p02/ti000 x1 input p121/ocd0a x2 ? connecting resonator for main system clock input port p122/exclk/ ocd0b exclk input external clock input for main system clock input port p122/x2/ocd0b v dd ? positive power supply ? ? v ss ? ground potential ? ? ocd0a p121/x1 ocd1a input p04/intp3 ocd0b p122/x2/exclk ocd1b ? connection for on-chip debug mode setting pins input port p05/intp2 note 38-pin products only chapter 2 pin functions user?s manual u18685ej3v0ud 24 2.2 description of pin functions 2.2.1 p00 to p07 (port 0) p00 to p07 function as an 8-bit i/o port. these pins also function as timer i/o, serial data i/o, external interrupt request input, remote control output, and the setting connection for on-chip debug mode. the following operation modes can be specified in 1-bit units. (1) port mode p00 to p07 function as an 8-bit i/o port. p00 to p07 can be set to input or output por t in 1-bit units using port mode register 0 (pm0). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). p00 to p06 can be set to n-ch open- drain output or cmos i/o in 1-bit uni ts using port output mode register 0 (pom0). p07 can be set to p-ch open-drain output or cmos i/o in 1-bit units using port output mode register 0 (pom0). this pin can be used as a carrier generator output fo r remote control by specifying p-ch open-drain output. (2) control mode p00 to p07 function as timer i/o, serial data i/o, exter nal interrupt request input, remote control output, and the setting connection for on-chip debug mode. (a) ti000 this is a pin for inputting an external count clock to 16 -bit timer/event counter 00 and is also for inputting a capture trigger signal to the ca pture registers (cr000, cr010) of 16-bit timer/event counter 00. (b) ti010 this is a pin for inputting a capture trigger signal to t he capture register (cr000) of 16-bit timer/event counter 00. (c) to00 this is a timer output pin of 16-bit timer/event counter 00. (d) rxd6 this is a serial data input pi n of serial interface uart6. (e) txd6 this is a serial data output pin of serial interface uart6. (f) ti50, ti51 these are the pins for inputting an external count clock to 8-bit timer/event counters 50 and 51. (g) to50, to51 these are the timer output pins of 8-it timer/event counters 50 and 51. (h) toh0, toh1 these are the timer output pins of 8-bit timers h0 and h1. chapter 2 pin functions user?s manual u18685ej3v0ud 25 (i) intp1 to intp3 these are external interrupt request input pins for wh ich the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (j) rem this is a pin for outputting remote control signal. (k) ocd1a, ocd1b these are the setting connection pins for on-chip debug mode. 2.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. these pins also function as pins for key interrupt input. the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. p10 to p17 can be set to input or output por t in 1-bit units using port mode register 1 (pm1). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). p10 to p17 can be set to n- ch open-drain output or cmos i/o in 1-bit units using port output mode register 1 (pom1). (2) control mode (a) kr0 to kr7 p10 to p17 function as key interrupt input. 2.2.3 p20 to p27 (port 2) p20 to p27 function as an 8-bit i/o port in the case of 38- pin products. p20 to p22, p25 to p27 function as a 6-bit i/o port in the case of 30-pin products. these pins also function as pins for exter nal interrupt request input. the following operation modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an 8-bit i/o port in the case of 38- pin products. p20 to p22, p25 to p27 function as a 6-bit i/o port in the case of 30-pin products. these pins can be set to input or out put port in 1-bit units using port mode register 2 (pm2). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 2 (pu2). these pins can be set to n-ch open-drain output or cmos i/o in 1-bit units using port output mode register 2 (pom2). (2) control mode (p27 only) (a) intp4 p27 functions as external interrupt request input pin. caution for the 30-pin products, be sure to set bits 3 and 4 of pm2 to ?1?, and bits 3 and 4 of p2, pu2, and pom2 to ?0?. remark p23 and p24 are provided to the 38-pin products only. chapter 2 pin functions user?s manual u18685ej3v0ud 26 2.2.4 p30 to p35 (port 3) (38-pin products only) p30 to p35 function as a 6-bit i/o port. these pins also function as pins for external interrupt request input and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p30 to p35 function as a 6-bit i/o port. p30 to p35 can be set to input or output port in 1-bit units using port mode register 3 (pm3). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). p30 to p35 can be set to n- ch open-drain output or cmos i/o in 1-bit units using port output mode register 3 (pom3). (2) control mode (a) kr9 to kr14 p30 to p35 function as key interrupt input. caution for the 30-pin products, be sure to set bits 0 to 5 of pm3 to ?1?, and bits 0 to 5 of p3, pu3, and pom3 to ?0?. 2.2.5 p120 to p123 (port 12) p120 to p122 function as a 3-bit i/o port. p123 functions as an input-only port. these pins al so function as pins for external interrupt request input, potential input for exter nal low-voltage detection, connecting resonator for main system clock, external clock input fo r main system clock, system reset inpu t, key interrupt input, and the setting connection for on-chip debug mode. when using the p123/reset/intp5/kr8 pin for p123, intp5, or kr8, set bit 3 (rstm) of reset pin mode register (rstmask) to ?1?. the following operation modes can be specified in 1-bit units. (1) port mode p120 to p122 function as a 3-bit i/o port. p123 functions as an input-only port. p120 to p122 can be set to input or output port in 1-bit units using port mode register 12 (pm12). only fo r p120 and p123, use of an on-chip pull- up resistor can be specified by pull-up resistor option re gister 12 (pu12). p120 to p122 can be set to n-ch open- drain output or cmos i/o in 1-bit units using port output mode register 12 (pom12). (2) control mode p120 to p123 function as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, external clock input for main system clock, system reset input, key interrupt input, and the setting connection for on-chip debug mode. (a) intp0, intp5 these are external interrupt request input pins for wh ich the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) exlvi this is a potential input pin for external low-voltage detection. (c) x1, x2 these are the pins for connecting a resonator for main system clock. chapter 2 pin functions user?s manual u18685ej3v0ud 27 (d) exclk this is an external clock inpu t pin for main system clock. (e) kr8 this is a key interrupt input pin. (f) reset this is the active-low system reset input pin. (g) ocd0a, ocd0b these are the setting connection pins for on-chip debug mode. 2.2.6 regc this is the pin for connecting regulator output (2.0 v) stabilization capacitance for internal operation. connect this pin to v ss via a capacitor (0.47 f: recommended). regc v ss caution keep the wiring length as short as possible for the broken- line part in the above figure. 2.2.7 v dd v dd is the positive power supply pin. 2.2.8 v ss v ss is the ground potential pin. 2.2.9 flmd0 this is a pin for setting flash memory programming mode. pull the flmd0 pin down by a resistor (100 k ? ) when executing the on-board prog ramming or self-programming. use flmd0 at the same level as v ss in the normal operation mode. in flash memory programming mode, connect this pin to the flash memory programmer. 2.3 pin i/o circuits and recommended connection of unused pins table 2-2 shows the types of pin i/o circuits and t he recommended connections of unused pins. see figure 2-1 for the configuration of the i/o circuit of each type. chapter 2 pin functions user?s manual u18685ej3v0ud 28 table 2-1. pin i/o circuit types pin name i/o circuit type i/o recommended connection of unused pins p00/ti51/to51 5-aq p01/toh0 5-ar p02/ti000/txd6 p03/ti010/to00/rxd6 p04/intp3/ocd1a p05/intp2/ocd1b p06/ti50/to50/intp1 5-aq p07/rem/toh1 5-as p10/kr0 p11/kr1 p12/kr2 p13/kr3 p14/kr4 p15/kr5 p16/kr6 p17/kr7 p20 p21 p22 p23 note 1 5-ar p24 note 1 p25 p26 p27/intp4 5-aq p30/kr9 note 1 p31/kr10 note 1 p32/kr11 note 1 p33/kr12 note 1 p34/kr13 note 1 p35/kr14 note 1 5-ar p120/exlvi/intp0 5-aq input: independently connect to v dd or v ss via a resistor. output: leave open. p121/x1/ocd0a p122/x2/exclk/ ocd0b 37 i/o input: independently connect to v dd or v ss via a resistor. output: leave open. p123/reset/kr8/ intp5 39 input connect to v dd directly or via a resistor. flmd0 38-a ? connect to v ss note 2 . notes 1. p23, p24, p30 to p35 are provided to 38-pin products only. 2. flmd0 is a pin that is used to write data to the flas h memory. to rewrite the data of the flash memory on- board, connect this pin to v ss via a resistor (100 k ? : recommended). chapter 2 pin functions user?s manual u18685ej3v0ud 29 figure 2-1. pin i/o circuit list (1/2) type 5-aq type 37 reset reset data output disable input enable v dd p-ch x1 n -ch v ss data output disable input enable v dd p-ch n -ch v ss p-ch n-ch x2 type 5-ar type 38-a type 5-as type 39 pullup enable v dd p-ch in input enable kr enable reset mask reset p123/kr8 intp5 input enable user?s manual u18685ej3v0ud 30 chapter 3 cpu architecture 3.1 memory space products in the pd179f11x, 179f12x microcontrollers can access a 64 kb memory space. figures 3-1 to 3-5 show the memory maps. caution regardless of the internal memory capacity, the initial value of the internal memory size switching register (ims) of all products in the pd179f11x, 179f12x microcont rollers is fixed (ims = cfh). therefore, set the value corr esponding to each product as indicated below. table 3-1. set values of internal memo ry size switching register (ims) flash memory version ( pd179f11x, 179f12x microcontrollers) ims rom capacity internal high-speed ram capacity pd179f110 41h 4 kb pd179f111 42h 8 kb 512 bytes pd179f112, 179f122 04h 16 kb 768 bytes pd179f113, 179f123 c6h 24 kb pd179f114, 179f124 c8h 32 kb 1 kb chapter 3 cpu architecture user?s manual u18685ej3v0ud 31 figure 3-1. memory map ( pd179f110) ffffh ff00h feffh fd00h fcffh 1000h 0fffh 0000h program memory space data memory space special function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits flash memory 4096 8 bits reserved vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1905 x 8 bits option byte area note 5 x 8 bits callf entry area 2048 x 8 bits 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 0fffh 0085h 0084h 008fh 008eh on-chip debug security id setting area note 10 x 8 bits note set the option bytes to 0080h to 0084h. set the on-chip debug security id to 0085h to 008eh. remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between addr ess values and block numbers in flash memory . block 00h block 01h block 03h 1 kb 0fffh 07ffh 0000h 0400h 03ffh 0c00h 0bffh block 02h chapter 3 cpu architecture user?s manual u18685ej3v0ud 32 figure 3-2. memory map ( pd179f111) ffffh ff00h feffh fd00h fcffh 2000h 1fffh 0000h program memory space data memory space special function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits flash memory 8192 8 bits reserved vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1905 x 8 bits option byte area note 5 x 8 bits callf entry area 2048 x 8 bits program area 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 0085h 0084h 1fffh 008fh 008eh on-chip debug security id setting area note 10 x 8 bits note set the option bytes to 0080h to 0084h. set the on-chip debug security id to 0085h to 008eh. remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between addr ess values and block numbers in flash memory . block 00h block 01h block 07h 1 kb 1fffh 07ffh 0000h 0400h 03ffh 1c00h 1bffh chapter 3 cpu architecture user?s manual u18685ej3v0ud 33 figure 3-3. memory map ( pd179f112, 179f122) ffffh ff00h feffh fc00h fbffh 4000h 3fffh 0000h program memory space data memory space special function registers (sfr) 256 8 bits internal high-speed ram 768 8 bits flash memory 16384 8 bits reserved vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1905 x 8 bits option byte area note 5 x 8 bits callf entry area 2048 x 8 bits program area 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 0085h 0084h 3fffh 008fh 008eh on-chip debug security id setting area note 10 x 8 bits note set the option bytes to 0080h to 0084h. set the on-chip debug security id to 0085h to 008eh. remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between addr ess values and block numbers in flash memory . block 00h block 01h block 0fh 1 kb 3fffh 07ffh 0000h 0400h 03ffh 3c00h 3bffh chapter 3 cpu architecture user?s manual u18685ej3v0ud 34 figure 3-4. memory map ( pd179f113, 179f123) ffffh ff00h feffh fb00h faffh 6000h 5fffh 0000h program memory space data memory space special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits reserved flash memory 24576 8 bits vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1905 x 8 bits option byte area note 5 x 8 bits callf entry area 2048 x 8 bits program area 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 0085h 0084h 5fffh 008fh 008eh on-chip debug security id setting area note 10 x 8 bits note set the option bytes to 0080h to 0084h. set the on-chip debug security id to 0085h to 008eh. remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between addr ess values and block numbers in flash memory . block 00h block 01h block 17h 1 kb 5fffh 07ffh 0000h 0400h 03ffh 5c00h 5bffh chapter 3 cpu architecture user?s manual u18685ej3v0ud 35 figure 3-5. memory map ( pd179f114, 179f124) ffffh ff00h feffh fb00h faffh 8000h 7fffh 0000h program memory space data memory space special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits reserved flash memory 32768 8 bits vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1905 x 8 bits option byte area note 5 x 8 bits callf entry area 2048 x 8 bits program area 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 0085h 0084h 7fffh 008fh 008eh on-chip debug security id setting area note 10 x 8 bits note set the option bytes to 0080h to 0084h. set the on-chip debug security id to 0085h to 008eh. remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between addr ess values and block numbers in flash memory . block 00h block 01h block 1fh 1 kb 7fffh 07ffh 0000h 0400h 03ffh 7c00h 7bffh chapter 3 cpu architecture user?s manual u18685ej3v0ud 36 correspondence between the address values and block num bers in the flash memory are shown below. table 3-2. correspondence between address va lues and block number s in flash memory address value block number address value block number 0000h to 03ffh 00h 4000h to 43ffh 10h 0400h to 07ffh 01h 4400h to 47ffh 11h 0800h to 0bffh 02h 4800h to 4bffh 12h 0c00h to 0fffh 03h 4c00h to 4fffh 13h 1000h to 13ffh 04h 5000h to 53ffh 14h 1400h to 17ffh 05h 5400h to 57ffh 15h 1800h to 1bffh 06h 5800h to 5bffh 16h 1c00h to 1fffh 07h 5c00h to 5fffh 17h 2000h to 23ffh 08h 6000h to 63ffh 18h 2400h to 27ffh 09h 6400h to 67ffh 19h 2800h to 2bffh 0ah 6800h to 6bffh 1ah 2c00h to 2fffh 0bh 6c00h to 6fffh 1bh 3000h to 33ffh 0ch 7000h to 73ffh 1ch 3400h to 37ffh 0dh 7400h to 77ffh 1dh 3800h to 3bffh 0eh 7800h to 7bffh 1eh 3c00h to 3fffh 0fh 7c00h to 7fffh 1fh remark pd179f110: block numbers 00h to 03h pd179f111: block numbers 00h to 07h pd179f112, 179f122: block numbers 00h to 0fh pd179f113, 179f123: block numbers 00h to 17h pd179f114, 179f124: block numbers 00h to 1fh chapter 3 cpu architecture user?s manual u18685ej3v0ud 37 3.1.1 internal program memory space the internal program memory space st ores the program and table data. normally, it is addressed with the program counter (pc). pd179f11x, 179f12x microcontrollers produc ts incorporate internal rom (flash memory), as shown below. table 3-3. internal rom capacity internal rom part number structure capacity pd179f110 4096 8 bits (0000h to 0fffh) pd179f111 8192 8 bits (0000h to 1fffh) pd179f112, 179f122 16384 8 bits (0000h to 3fffh) pd179f113, 179f123 24576 8 bits (0000h to 5fffh) pd179f114, 179f124 flash memory 32768 8 bits (0000h to 7fffh) the internal program memory space is divided into the following areas. (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vect or table area. the pr ogram start addresses for branch upon reset or generation of each interrupt r equest are stored in the ve ctor table area. of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. table 3-4. vector table vector table address interrupt source vector table address interrupt source 0000h reset input, poc, lvi, wdt 0016h intst6 0004h intlvi 001ah inttmh1 0006h intp0 001ch inttmh0 0008h intp1 001eh inttm50 000ah intp2 0020h inttm000 000ch intp3 0022h inttm010 000eh intp4 002ah inttm51 0010h intp5 002ch intkr 0012h intsre6 002eh intwt 0014h intsr6 003eh brk (2) callt instruction table area the 64-byte area 0040h to 007fh can stor e the subroutine entry address of a 1-byte call instruction (callt). (3) option byte area a 5-byte area of 0080h to 0084h can be used as an option byte area. for details, see chapter 17 option byte . (4) callf instruction entry area the area 0800h to 0fffh can perform a direct subrout ine call with a 2-byte ca ll instruction (callf). chapter 3 cpu architecture user?s manual u18685ej3v0ud 38 (5) on-chip debug security id setting area a 10-byte area of 0085h to 008eh can be used as an on-ch ip debug security id setting area. for details, see chapter 19 on-chip debug function . 3.1.2 internal data memory space pd179f11x, 179f12x microcontrollers incorporate the following rams. (1) internal high-speed ram table 3-5. internal high-speed ram capacity part number internal high-speed ram pd179f110 pd179f111 512 8 bits (fd00h to feffh) pd179f112, 179f122 768 8 bits (fc00h to feffh) pd179f113, 179f123 pd179f114, 179f124 1024 8 bits (fb00h to feffh) the 32-byte area fee0h to feffh is assigned to four general-purpose register ban ks consisting of eight 8- bit registers per bank. this area cannot be used as a program area in which instructions ar e written and executed. the internal high-speed ram can also be used as a stack memory. 3.1.3 special function register (sfr) area on-chip peripheral hardware special f unction registers (sfrs) are alloca ted in the area ff00h to ffffh (see table 3-6 special function register list in 3.2.3 special function registers (sfrs) ). caution do not access addresses to which sfrs are not assigned. 3.1.4 data memory addressing addressing refers to the method of s pecifying the address of the instruction to be execut ed next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memory relevant to the executi on of instructions for the pd179f11x, 179f12x microcontrollers, bas ed on operability and other c onsiderations. for areas containing data memory in particular, special addressing methods designed fo r the functions of special function registers (sfr) and general-purpose registers are available for use. figures 3-6 to 3-10 s how correspondence between data memory and addressing. for details of each addressing mode, see 3.4 operand address addressing . chapter 3 cpu architecture user?s manual u18685ej3v0ud 39 figure 3-6. correspondence between data memory and addressing ( pd179f110) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fe20h fe1fh fd00h fcffh 1000h 0fffh internal high-speed ram 512 8 bits reserved flash memory 4096 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing chapter 3 cpu architecture user?s manual u18685ej3v0ud 40 figure 3-7. correspondence between data memory and addressing ( pd179f111) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fe20h fe1fh fd00h fcffh 2000h 1fffh internal high-speed ram 512 8 bits reserved flash memory 8192 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing chapter 3 cpu architecture user?s manual u18685ej3v0ud 41 figure 3-8. correspondence between data memory and addressing ( pd179f112 and 179f122) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fe20h fe1fh fc00h fbffh 4000h 3fffh internal high-speed ram 768 8 bits reserved flash memory 16384 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing chapter 3 cpu architecture user?s manual u18685ej3v0ud 42 figure 3-9 . correspondence between data memory and addressing ( pd179f113 and 179f123) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fe20h fe1fh fb00h faffh 6000h 5fffh internal high-speed ram 1024 8 bits reserved flash memory 24576 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing chapter 3 cpu architecture user?s manual u18685ej3v0ud 43 figure 3-10. correspondence between data memory and addressing ( pd179f114 and 179f124) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fe20h fe1fh fb00h faffh 8000h 7fffh internal high-speed ram 1024 8 bits reserved flash memory 32768 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing chapter 3 cpu architecture user?s manual u18685ej3v0ud 44 3.2 processor registers the pd179f11x, 179f12x microcontrollers incorpor ate the following processor registers. 3.2.1 control registers the control registers control the program sequence, st atuses and stack memory. the c ontrol registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit r egister that holds the address info rmation of the next program to be executed. in normal operation, pc is automatica lly incremented according to the number of bytes of the instruction to be fetched. when a branch instruct ion is executed, immediate dat a and register contents are set. reset signal generation sets the reset vector tabl e values at addresses 0000h and 0001h to the program counter. figure 3-11. format of program counter 15 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags set/reset by instruction execution. program status word contents are stored in the stack area upon interr upt request generation or push psw instruction execution and are rest ored upon execution of the retb, reti and pop psw instructions. reset signal generation sets psw to 02h. figure 3-12. format of program status word ie z rbs1 ac rbs0 isp cy 70 0 psw (a) interrupt enable flag (ie) this flag controls the interrupt reques t acknowledge operations of the cpu. when 0, the ie flag is set to the interrupt disabl ed (di) state, and all mask able interrupt requests are disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request acknowledgment is controlled with an in-service priority flag (isp), an in terrupt mask flag for various interrupt sources, and a priority specification flag. the ie flag is reset (0) upon di instruction executi on or interrupt acknowledgment and is set (1) upon ei instruction execution. chapter 3 cpu architecture user?s manual u18685ej3v0ud 45 (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates the register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable mask able vectored interrupts. when this flag is 0, low-level vectored interrupt requests specified by a priority specific ation flag register (pr0l, pr0h, pr1l) (see 11.3 (3) priority spec ification flag registers (pr0l, pr 0h, pr1l)) can not be acknowledged. actual request acknowledgment is contro lled by the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underfl ow upon add/subtract instruction exec ution. it stores the shift-out value upon rotate instruction execut ion and functions as a bit accumula tor during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of t he memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-13. format of stack pointer 15 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-14 and 3-15. caution since reset signal generation makes the sp c ontents undefined, be sure to initialize the sp before using the stack. chapter 3 cpu architecture user?s manual u18685ej3v0ud 46 figure 3-14. data to be saved to stack memory (a) push rp instruction (when sp = fee0h) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) call, callf, callt instructions (when sp = fee0h) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) interrupt, brk instructions (when sp = fee0h) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh chapter 3 cpu architecture user?s manual u18685ej3v0ud 47 figure 3-15. data to be restored from stack memory (a) pop rp instruction (when sp = fedeh) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) ret instruction (when sp = fedeh) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) reti, retb instructions (when sp = feddh) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh chapter 3 cpu architecture user?s manual u18685ej3v0ud 48 3.2.2 general-purpose registers general-purpose registers are mapped at particular addresses (fee0h to feffh) of the data memory. the general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit regi sters (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit r egister, and two 8-bit registers can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set by the cpu control instruction (sel rbn). because of the 4-register bank configur ation, an efficient program can be created by switching bet ween a register for normal processing and a register for interrupts for each bank. figure 3-16. configuration of general-purpose registers (a) function name register bank 0 register bank 1 register bank 2 register bank 3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h (b) absolute name register bank 0 register bank 1 register bank 2 register bank 3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h chapter 3 cpu architecture user?s manual u18685ej3v0ud 49 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special function register has a special function. sfrs are allocated to the ff00h to ffffh area. special function registers can be m anipulated like general-purpose registers, using operat ion, transfer, and bit manipulation instructions. the mani pulatable bit units, 1, 8, and 16, depend on the special function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1-bit manipulation inst ruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler fo r the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler fo r the 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-6 gives a list of the special function registers. the meanings of items in the table are as follows. ? symbol symbol indicating the address of a s pecial function register. it is a rese rved word in the ra78k0, and is defined as an sfr variable using the #pragma sfr directive in the cc78k0. w hen using the ra78k0, id78k0-qb, and sm+ for 78k0/kx2, symbols can be wr itten as an instruction operand. ? r/w indicates whether the corresponding special function register can be read or written. r/w: read/write enable r: read only w: write only ? manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register stat us upon reset signal generation. chapter 3 cpu architecture user?s manual u18685ej3v0ud 50 table 3-6. special function register list (1/3) manipulatable bit unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port register 0 p0 r/w ? 00h ff01h port register 1 p1 r/w ? 00h ff02h port register 2 p2 r/w ? 00h ff03h port register 3 p3 r/w ? 00h ff0ah receive buffer register 6 rxb6 r ? ? ffh ff0bh transmit buffer register 6 txb6 r/w ? ? ffh ff0ch port register 12 p12 r/w ? 00h ff10h ff11h 16-bit timer counter 00 tm00 r ? ? 0000h ff12h ff13h 16-bit timer capture/compare register 000 cr000 r/w ? ? 0000h ff14h ff15h 16-bit timer capture/compare register 010 cr010 r/w ? ? 0000h ff16h 8-bit timer counter 50 tm50 r ? ? 00h ff17h 8-bit timer compare register 50 cr50 r/w ? ? 00h ff18h 8-bit timer h compare register 00 cmp00 r/w ? ? 00h ff19h 8-bit timer h compare register 10 cmp10 r/w ? ? 00h ff1ah 8-bit timer h compare register 01 cmp01 r/w ? ? 00h ff1bh 8-bit timer h compare register 11 cmp11 r/w ? ? 00h ff1fh 8-bit timer counter 51 tm51 r ? ? 00h ff20h port mode register 0 pm0 r/w ? ffh ff21h port mode register 1 pm1 r/w ? ffh ff22h port mode register 2 pm2 r/w ? ffh ff23h port mode register 3 pm3 r/w ? ffh ff2ch port mode register 12 pm12 r/w ? ffh ff2eh reset pin mode register rstmask r/w ? 00h ff30h pull-up resistor option register 0 pu0 r/w ? 00h ff31h pull-up resistor option register 1 pu1 r/w ? 00h ff32h pull-up resistor option register 2 pu2 r/w ? 00h ff33h pull-up resistor option register 3 pu3 r/w ? 00h ff35h flmd0 pull-up/pull-down c ontrol register fpctl r/w ? 00h ff37h flmd0 pull-up/pull-down enable register fpen r/w ? 00h ff38h port output mode resistor 0 pom0 r/w ? 00h ff39h port output mode resistor 1 pom1 r/w ? 00h ff3ah port output mode resistor 2 pom2 r/w ? 00h ff3bh port output mode resistor 3 pom3 r/w ? 00h ff3ch pull-up resistor option register 12 pu12 r/w ? 08h ff3eh port output mode resistor 12 pom12 r/w ? 00h ff41h 8-bit timer compare register 51 cr51 r/w ? ? 00h ff43h 8-bit timer mode control register 51 tmc51 r/w ? 00h ff48h external interrupt ri sing edge enable register egp r/w ? 00h ff49h external interrupt fa lling edge enable register egn r/w ? 00h chapter 3 cpu architecture user?s manual u18685ej3v0ud 51 table 3-6. special function register list (2/3) manipulatable bit unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff50h asynchronous serial interface operation mode register 6 asim6 r/w ? 01h ff53h asynchronous serial interface reception error status register 6 asis6 r ? ? 00h ff55h asynchronous serial interface transmission status register 6 asif6 r ? ? 00h ff56h clock selection register 6 cksr6 r/w ? ? 00h ff57h baud rate generator control register 6 brgc6 r/w ? ? ffh ff58h asynchronous serial interfac e control register 6 asicl6 r/w ? 16h ff69h 8-bit timer h mode register 0 tmhmd0 r/w ? 00h ff6ah timer clock selection register 50 tcl50 r/w ? 00h ff6bh 8-bit timer mode control register 50 tmc50 r/w ? 00h ff6ch 8-bit timer h mode register 1 tmhmd1 r/w ? 00h ff6dh 8-bit timer h carrier cont rol register 1 tmcyc1 r/w ? 00h ff6eh key return mode register 0 krml r/w ? 00h ff6fh key return mode register 1 krmh r/w ? 00h ff8ch timer clock selection register 51 tcl51 r/w ? 00h ff99h watchdog timer enable register wdte r/w ? ? note 1 1ah/9ah ff9fh clock operation mode select register oscctl r/w ? 00h ffa0h internal oscillation mode register rcm r/w ? 80h note 2 ffa1h main clock mode register mcm r/w ? 00h ffa2h main osc control register moc r/w ? 80h ffa3h oscillation stabilization time counter status register ostc r ? 00h ffa4h oscillation stabilization time select register osts r/w ? ? 05h ffach reset control flag register resf r ? ? 00h note 3 ffb0h ram data retention control register lvdet r/w ? undefined ffbah 16-bit timer mode control register 00 tmc00 r/w ? 00h ffbbh prescaler mode register 00 prm00 r/w ? 00h ffbch capture/compare control register 00 crc00 r/w ? 00h ffbdh 16-bit timer output control register 00 toc00 r/w ? 00h ffbeh low-voltage detection register lvim r/w ? 00h note 3 ffbfh low-voltage detection level selection register lvis r/w ? 00h note 3 ffe0h interrupt request flag register 0l if0 if0l r/w 00h ffe1h interrupt request flag register 0h if0h r/w 00h ffe2h interrupt request flag register 1l if1 if1l r/w ? 00h ffe4h interrupt mask flag register 0l mk0 mk0l r/w ffh ffe5h interrupt mask flag register 0h mk0h r/w ffh ffe6h interrupt mask flag register 1l mk1 mk1l r/w ? ffh notes 1. the reset value of wdte is determined by setting of option byte. 2. the value of this register is 00h immediately afte r a reset release but automatically changes to 80h after oscillation accuracy stabilization of hi gh-speed internal oscillator has been waited. 3. the reset values of resf, lvim, and lvis vary depending on the reset source. chapter 3 cpu architecture user?s manual u18685ej3v0ud 52 table 3-6. special function register list (3/3) manipulatable bit unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffe8h priority specificati on flag register 0l pr0l r/w ffh ffe9h priority specific ation flag register 0h pr0 pr0h r/w ffh ffeah priority spec ification flag register 1l pr1 pr1l r/w ? ffh fff0h internal memory size switching register note ims r/w ? ? cfh fff9h internal high-speed oscillator trimming register r4mtrm2 r/w ? ? 00h fffbh processor clock control register pcc r/w ? 01h note regardless of the internal memory c apacity, the initial value of the internal memory size switching register (ims) of all products in the pd179f11x, 179f12x microcontrollers is fix ed (ims = cfh). therefore, set the value corresponding to each product as indicated below. flash memory version ( pd179f11x, 179f12x microcontrollers) ims rom capacity internal high-speed ram capacity pd179f110 41h 4 kb pd179f111 42h 8 kb 512 bytes pd179f112, 179f122 04h 16 kb 768 bytes pd179f113, 179f123 c6h 24 kb pd179f114, 179f124 c8h 32 kb 1 kb chapter 3 cpu architecture user?s manual u18685ej3v0ud 53 3.3 instruction address addressing an instruction address is determined by contents of the program counter (pc), and is normally incremented (+1 for each byte) automatically according to t he number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, t he branch destination information is set to pc and branched by the following addressing (for details of instructions, refer to the 78k/0 series instructions user?s manual (u12326e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immedi ate data (displacement value: jdis p8) of an instruction code to the start address of the following instruction is transfe rred to the program counter (pc) and branched. the displacement value is treated as signed two?s complement data ( ? 128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists of rela tive branching from the st art address of the following instruction to the ? 128 to +127 range. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ... chapter 3 cpu architecture user?s manual u18685ej3v0ud 54 3.3.2 immediate addressing [function] immediate data in the instructi on word is transferred to the pr ogram counter (pc) and branched. this function is carried out when t he call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instru ctions can be branched to the entire memory space. the callf !addr11 instruct ion is branched to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10?8 11 10 00001 643 callf fa 7?0 chapter 3 cpu architecture user?s manual u18685ej3v0ud 55 3.3.3 table indirect addressing [function] table contents (branch destinat ion address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation c ode are transferred to the progr am counter (pc) and branched. this function is carried out when the ca llt [addr5] instruct ion is executed. this instruction references the addre ss that is indicated by addr5 and is st ored in the memory table from 0040h to 007fh, and allows branching to the entire memory space. [illustration] pc 15 0 8 7 70 low addr. high addr. memory (table) effective address 15 0 5 8 1 0000000001 0 operation code 7 0 1 6 5 11 1 ta 4-0 effective address+1 76 addr5 15 0 5 1 0000000001 0 6 ta 4-0 the value of the effective address is the same as that of addr5. ... 3.3.4 register addressing [function] register pair (ax) contents to be spec ified with an instruction word are trans ferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 chapter 3 cpu architecture user?s manual u18685ej3v0ud 56 3.4 operand address addressing the following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register that functions as an accumulator (a and ax) among the gener al-purpose registers is automatically (implicitly) addressed. of the pd179f11x, 179f12x microcontrollers in struction words, the following instructions employ implied addressing. instruction register to be s pecified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for stor age of numeric values that become decimal correction targets ror4/rol4 a register for storage of digit data that undergoes digit rotation [operand format] because implied addressing can be autom atically determined with an instruct ion, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the pr oduct of a register and x register is stored in ax. in this example, the a and ax registers are spec ified by implied addressing. chapter 3 cpu architecture user?s manual u18685ej3v0ud 57 3.4.2 register addressing [function] the general-purpose register to be s pecified is accessed as an operand with the register bank select flags (rbs0 to rbs1) and the register s pecify codes of an operation code. register addressing is carried out when an instruction with the following operand forma t is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described by absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 0 1100010 register specify code incw de; when selecting de register pair as rp operation code 1 0000100 register specify code chapter 3 cpu architecture user?s manual u18685ej3v0ud 58 3.4.3 direct addressing [function] the memory to be manipulated is di rectly addressed with immediate data in an instruction word becoming an operand address. this addressing can be carried out for all of the memory spaces. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 1 0001110 op c ode 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code chapter 3 cpu architecture user?s manual u18685ej3v0ud 59 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit dat a in an instruction word. this addressing is applied to the 256-byte space fe 20h to ff1fh. internal high-speed ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addre ssing is applied is a part of the overall sfr area. ports that are frequently accessed in a program and compare and c apture registers of t he timer/event counter are mapped in this area, allowing sfrs to be m anipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see the [illustration] shown below. [operand format] identifier description saddr immediate data that indica te label or fe20h to ff1fh saddrp immediate data that indicate label or fe20h to ff1fh (even address only) [description example] lb1 equ 0fe30h ; defines fe30h by lb1. : mov lb1, a ; when lb1 indicates fe30h of the saddr area and the value of regist er a is transferred to that address operation code 1 1110010 op c ode 00110000 30h (s addr-offset) [illustration] 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 chapter 3 cpu architecture user?s manual u18685ej3v0ud 60 3.4.5 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with 8-bit immediate dat a in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be acce ssed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special func tion register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 1 1110110 op c ode 0 0100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 chapter 3 cpu architecture user?s manual u18685ej3v0ud 61 3.4.6 register indirect addressing [function] register pair contents specified by a register pair specify code in an inst ruction word and by a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory. this addressing can be carried out for all of the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 1 0000101 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de chapter 3 cpu architecture user?s manual u18685ej3v0ud 62 3.4.7 based addressing [function] 8-bit immediate data is added as offset dat a to the contents of the base register, that is, t he hl register pair in the register bank specified by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all of the memory spaces. [operand format] identifier description ? [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 1 0101110 00010000 [illustration] 16 0 8 h 7 l 0 7 7 0 a hl the contents of the memory addressed are transferred. memory +10h chapter 3 cpu architecture user?s manual u18685ej3v0ud 63 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the base register, that is, the hl register pair in the regi ster bank specified by t he register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is perfo rmed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all of the memory spaces. [operand format] identifier description ? [hl + b], [hl + c] [description example] mov a, [hl +b]; when selecting b register operation code 1 0101011 [illustration] 16 0 h 7 8 l 0 7 b + 0 7 7 0 a hl the contents of the memory addressed are transferred. memory chapter 3 cpu architecture user?s manual u18685ej3v0ud 64 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatic ally employed when the push, po p, subroutine call, and return instructions are executed or t he register is saved/reset upon generation of an interrupt request. with stack addressing, only the inter nal high-speed ram area can be accessed. [description example] push de; when saving de register operation code 1 0110101 [illustration] e fee0h sp sp fee0h fedfh fedeh d memory 0 7 fedeh user?s manual u18685ej3v0ud 65 chapter 4 port functions 4.1 port functions pd179f11x, 179f12x microcontrollers are provided with the ports shown in figure 4-1, which enable variety of control operations. the functions of each port are shown in table 4-1. in addition to the func tion as digital i/o ports, these ports have several alternate f unctions. for details of the alternate functions, see chapter 2 pin functions . figure 4-1. port types p30 p35 p120 p123 p20 p10 p17 p00 p07 p27 p23 note p24 note port 3 note port 12 port 0 port 2 port 1 note 38-pin products only chapter 4 port functions user?s manual u18685ej3v0ud 66 table 4-1. port functions function name i/o function after reset alternate function p00 ti51/to51 p01 toh0 p02 ti000/txd6 p03 ti010/to00/ r x d6 p04 intp3/ocd1a p05 intp2/ocd1b p06 ti50/to50/intp1 p07 i/o port 0. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified in 1-bit units. p00 to p06 can be set to n-ch open-drain output or cmos i/o in 1-bit units. p07 can be set to p-ch open-drain output or cmos i/o in 1-bit units. this pin can be used as a carrier generator output for remote control by specifying p-ch open-drain output. input port rem/toh1 p10 to p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified in 1-bit units. p10 to p17 can be set to n-ch open-drain output or cmos i/o in 1-bit units. input port kr0 to kr7 p20 to p22 ? p23 note , p24 note ? p25, p26 ? p27 i/o port 2. 38-pin products: 8-bit i/o port 30-pin products: 6-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified in 1-bit units. p20 to p22, p23 note , p24 note , p25 to p27 can be set to n-ch open-drain output or cmos i/o in 1-bit units. input port intp4 p30 to p35 note i/o port 3 note . 6-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified in 1-bit units. p30 to p35 can be set to n-ch open-drain output or cmos i/o in 1-bit units. input port kr9 to kr14 note p120 exlvi/intp0 p121 x1/ocd0a p122 i/o x2/exclk/ocd0b p123 input port 12. 3-bit i/o port and 1-bit input-only port. input/output can be specified in 1-bit units in p120 to p122. use of an on-chip pull-up resistor can be specified in only p120 and p123. p120 to p122 can be set to n- ch open-drain output or cmos i/o in 1-bit units. input port reset/kr8/ intp5 note 38-pin products only. for the 30-pin products, be sure to set bits 3 and 4 of pm 2, bits 0 to 5 of pm3 to ?1?, and bits 3 and 4 of p2, pu2, and pom2, bits 0 to 5 of p3, pu3, and pom3 to ?0?. chapter 4 port functions user?s manual u18685ej3v0ud 67 4.2 port configuration ports include the following hardware. table 4-2. port configuration item configuration control registers port mode register (pm0 to pm2, pm3 note , pm12) port register (p0 to p2, p3 note , p12) pull-up resistor option register (pu0 to pu2, pu3 note , pu12) port output mode register (pom0 to pom2, pom3 note , pom12) reset pin mode register (rstmask) port ? 30-pin products total: 26 (n-ch open drain output or cmos i/o: 24, p-ch open drain output or cmos i/o: 1, cmos input: 1) ? 38-pin products total: 34 (n-ch open drain output or cmos i/o: 32, p-ch open drain output or cmos i/o: 1, cmos input: 1) pull-up resistor ? 30-pin products total: 24 ? 38-pin products total: 32 note 38-pin products only chapter 4 port functions user?s manual u18685ej3v0ud 68 4.2.1 port 0 port 0 is an 8-bit i/o port with an output latch. port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). when the p00 to p07 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (pu0). p00 to p06 can be set to n-ch open-drain output or cmos i/o in 1-bit units using port output mode register 0 (pom0). p07 can be set to p-ch open-drain output or cmos i/o in 1-bit units using port output mode register 0 (pom0). this pin can be used as a carrier generator output fo r remote control by specifying p-ch open-drain output. this port can also be used for timer i/o, serial data i/o, exte rnal interrupt request inpu t, remote control output, and the setting connection for on-chip debug mode. reset signal generation sets port 0 to input mode. figures 4-2 to 4-6 show block diagrams of port 0. figure 4-2. block diagram of p00 and p03 wr pu rd wr port wr pm pu00, pu03 pm00, pm03 v dd p-ch pu0 pm0 p0 p00/ti51/to51, p03/ti010/to00/ r x d6 pom00, pom03 pom0 internal bus alternate function output latch (p00, p03) alternate function selector wr pom note p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 pom0: port output mode register 0 rd: read signal wr : write signal note output buffer which can be switched to cmos output or n-ch open-drain output chapter 4 port functions user?s manual u18685ej3v0ud 69 figure 4-3. block diagram of p01 and p07 p01/toh0, p07/rem/toh1 wr pu rd wr port wr pm pu01, pu07 pm01, pm07 v dd p-ch pu0 pm0 p0 pom01, pom07 pom0 internal bus alternate function output latch (p01, p07) selector wr pom note p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 pom0: port output mode register 0 rd: read signal wr : write signal note for the p01, output buffer which can be swit ched to cmos output or n-ch open-drain output. for the p07, output buffer which can be swit ched to cmos output or p-ch open-drain output. chapter 4 port functions user?s manual u18685ej3v0ud 70 figure 4-4. block diagram of p02 p02/ti000/txd6 wr pu rd wr port wr pm pu02 pm02 v dd p-ch pu0 pm0 p0 pom02 pom0 internal bus alternate function alternate function output latch (p02) selector wr pom note p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 pom0: port output mode register 0 rd: read signal wr : write signal note output buffer which can be switched to cmos output or n-ch open-drain output chapter 4 port functions user?s manual u18685ej3v0ud 71 figure 4-5. block diagram of p04 and p05 wr pu rd wr port wr pm pu04, pu05 pm04, pm05 v dd p-ch pu0 pm0 p0 pom04, pom05 pom0 internal bus alternate function output latch (p04, p05) selector wr pom note p04/intp3/ocd1a p05/intp2/ocd1b p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 pom0: port output mode register 0 rd: read signal wr : write signal note output buffer which can be switched to cmos output or n-ch open-drain output chapter 4 port functions user?s manual u18685ej3v0ud 72 figure 4-6. block diagram of p06 p06/ti50/to50/intp1 wr pu rd wr port wr pm pu06 pm06 v dd p-ch pm0 pu0 p0 pom06 pom0 internal bus alternate function alternate function output latch (p06) selector wr pom note p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 pom0: port output mode register 0 rd: read signal wr : write signal note output buffer which can be switched to cmos output or n-ch open-drain output chapter 4 port functions user?s manual u18685ej3v0ud 73 4.2.2 port 1 port 1 is an 8-bit i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (p u1). p10 to p17 can be set to n-ch open- drain output or cmos i/o in 1-bit units us ing port output mode register 1 (pom1). this port can also be used for key interrupt input. reset signal generation sets port 1 to input mode. figure 4-7 show block diagrams of port 1. figure 4-7. block diagram of p10 to p17 p10/kr0 to p17/kr7 wr pu rd wr port wr pm pu10 to pu17 pm10 to pm17 v dd p-ch pu1 pm1 p1 pom10 to pom17 pom1 internal bus alternate function output latch (p10 to p17) selector wr pom note p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 pom1: port output mode register 1 rd: read signal wr : write signal note output buffer which can be switched to cmos output or n-ch open-drain output chapter 4 port functions user?s manual u18685ej3v0ud 74 4.2.3 port 2 port 2 is a 6-bit i/o port with an output latch for 30-pin pro ducts. port 2 is an 8-bit i/o port with an output latch for 38-pin products. port 2 can be set to the input mode or out put mode in 1-bit units using port mode register 0 (pm2). when the p20 to p27 pins are used as an input port, use of an on-chip pull-up re sistor can be specified in 1-bit units by pull-up resistor option regi ster 2 (pu2). these pins can be set to n-ch open-drain output or cmos i/o in 1-bit units using port output mode register 2 (pom2). only p27 can also be used for external interrupt request input. reset signal generation sets port 2 to input mode. figures 4-8 to 4-10 show block diagrams of port 2. remark 30-pin products: p20 to p22, p25, p26, p27/intp4 38-pin products: p20 to p26, p27/intp4 figure 4-8. block diagram of p20 to p23 rd p-ch wr pu wr port wr pm pu20 to pu22, pu23 note1 pm20 to pm22, pm23 note1 v dd pu2 pm2 p2 pom20 to pom22, pom23 note1 pom2 internal bus output latch (p20 to p22, p23 note1 ) selector p20 to p22, p23 note1 wr pom note2 p2: port register 2 pm2: port mode register 2 pom2: port output mode register 2 rd: read signal wr : write signal notes 1. 38-pin products only 2. output buffer which can be switched to cmos output or n-ch open-drain output chapter 4 port functions user?s manual u18685ej3v0ud 75 figure 4-9. block diagram of p24 to p26 rd p-ch wr pu wr port wr pm pu20 to pu22, pu23 note1 pm20 to pm22, pm23 note1 v dd pu2 pm2 p2 pom20 to pom22, pom23 note1 pom2 internal bus output latch (p20 to p22, p23 note1 ) selector wr pom p24 note1 , p25, p26 note2 p2: port register 2 pm2: port mode register 2 pom2: port output mode register 2 rd: read signal wr : write signal notes 1. 38-pin products only 2. output buffer which can be switched to cmos output or n-ch open-drain output chapter 4 port functions user?s manual u18685ej3v0ud 76 figure 4-10. blo ck diagram of p27 p27/intp4 wr pu rd wr port wr pm pu27 pm27 v dd p-ch pu2 pm2 p2 pom27 pom2 internal bus alternate function output latch (p27) selector wr pom note p2: port register 2 pm2: port mode register 2 pom2: port output mode register 2 rd: read signal wr : write signal note output buffer which can be switched to cmos output or n-ch open-drain output chapter 4 port functions user?s manual u18685ej3v0ud 77 4.2.4 port 3 (38-pin products only) port 3 is a 6-bit i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm3). when the p30 to p35 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (p u3). p30 to p35 can be set to n-ch open- drain output or cmos i/o in 1-bit units using port output mode register 3 (pom3). this port can also be used for key interrupt input. reset signal generation sets port 3 to input mode. figure 4-11 show block diagrams of port 3. figure 4-11. block di agram of p30 to p35 p30/kr9 to p35/kr14 wr pu rd wr port wr pm pu30 to pu35 pm30 to pm35 v dd p-ch pu3 pm3 p3 pom30 to pom35 pom3 internal bus alternate function output latch (p30 to p35) selector wr pom note p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 pom3: port output mode register 3 rd: read signal wr : write signal note output buffer which can be switched to cmos output or n-ch open-drain output chapter 4 port functions user?s manual u18685ej3v0ud 78 4.2.5 port 12 p120 to p122 are a 3-bit i/o port, and p123 is an input-only port. p120 to p122 can be set to the input mode or output mode in 1-bit units using port mode register 12 (p m12). when used as an input port only for p120 and p123, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). p120 to p122 can be set to n-ch open-drain output or cmos i/o in 1-bi t units using port output mode register 12 (pom12). this port can also be used as pins for external interru pt request input, potential input for external low-voltage detection, connecting resonator for main system clock, external clock input for main system clock, system reset input, key interrupt input, and the setting connection for on-chip debug mode. reset signal generation sets port 12 to input mode. figures 4-12 and 4-14 show block diagrams of port 12. caution when using the p121 and p122 pins to connect a resonator for the main system clock (x1, x2), or to input an external clock for the main system clock (exclk ), the x1 oscillation mode, or external clock input mode must be set by us ing the clock operation mode select register (oscctl) (for details, see 5.3 (1) clock operation mode select register (oscctl)). the reset value of oscctl is 00h (all of the p121 and p122 pi ns are i/o port pins). at this time, setting of the pm121, pm122, p121, and p122 pins is not necessary. figure 4-12. blo ck diagram of p120 p120/exlvi/intp0 wr pu rd wr port wr pm pu120 pm120 v dd p-ch pu12 pm12 p12 pom120 pom12 internal bus alternate function output latch (p120) selector wr pom note p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 pom12: port output mode register 12 rd: read signal wr : write signal note output buffer which can be switched to cmos output or n-ch open-drain output chapter 4 port functions user?s manual u18685ej3v0ud 79 figure 4-13. block di agram of p121 and p122 p122/x2/exclk/ocd0b rd wr port wr pm pm122 pm12 p12 rd wr port wr pm pm121 pm12 p12 exclk, oscsel oscctl oscsel oscctl p121/x1/ocd0a oscsel oscctl oscsel oscctl pom122 pom12 pom121 pom12 internal bus output latch (p121) selector output latch (p122) selector wr pom note note wr pom p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 oscctl: clock operation mode select register rd: read signal wr : write signal note output buffer which can be switched to cmos output or n-ch open-drain output chapter 4 port functions user?s manual u18685ej3v0ud 80 figure 4-14. blo ck diagram of p123 p123/reset/kr8/intp5 wr pu rd pu123 v dd p-ch pu12 internal bus alternate function rstm rstmask wr pm internal reset pu12: pull-up resistor option register 12 rstmask: reset pin mode register rd: read signal wr : write signal remark after reset, reset function and pull-up re sistor are enabled (rstm = 0, pu123 = 1). when using the p123/reset/kr8/intp5 pin for p123, kr8, or intp5 set rstm to ?1?. chapter 4 port functions user?s manual u18685ej3v0ud 81 4.3 registers controlling port function port functions are controlled by the following five types of registers. ? port mode registers (pm0 to pm2, pm3 note , pm12) ? port registers (p0 to p2, p3 note , p12) ? pull-up resistor option registers (pu0 to pu2, pu3 note , pu12) ? port output mode registers (pom0 to pom2, pom3 note , pom12) ? reset pin mode register (rstmask) note 38-pin products only (1) port mode registers (pm0 to pm2, pm3 note , pm12) these registers specify input or output mode for the port in 1-bit units. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. when port pins are used as alternate-function pi ns, set the port mode register by referencing 4.5 settings of port mode register, output latch, pull-up resistor option register, and port output mode register when using alternate function . note 38-pin products only figure 4-15. format of port mode register 7 pm07 symbol pm0 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 address ff20h after reset ffh r/w r/w pm17 pm1 pm16 pm15 pm14 pm13 pm12 pm11 pm10 ff21h ffh r/w pm27 pm2 pm26 pm25 pm24 note pm23 note pm22 pm21 pm20 ff22h ffh r/w 1 pm3 note 1 pm35 note pm34 note pm33 note pm32 note pm31 note pm30 note ff23h ffh r/w 1 pm12 1 1 1 1 pm122 pm121 pm120 ff2ch ffh r/w pmmn pmn pin i/o mode selection (m = 0 to 3, 12; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) note 38-pin products only caution for the 30-pin products, be su re to set bits 3 and 4 of pm2, bits 0 to 5 of pm3 to ?1?. chapter 4 port functions user?s manual u18685ej3v0ud 82 (2) port registers (p0 to p2, p3 note , and p12) these registers write the data t hat is output from the chip when data is output from a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the value of the output latch is read. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to 00h. note 38-pin products only figure 4-16. format of port register 7 0 symbol p0 6 0 5 0 4 0 3 0 2 0 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w p17 p1 p16 p15 p14 p13 p12 p11 p10 ff01h 00h (output latch) r/w r/w p27 p2 p26 p25 p24 note p23 note p22 p21 p20 ff02h 00h (output latch) 0 p3 note 0 p35 note p34 note p33 note p32 note p31 note p30 note ff03h 00h (output latch) r/w 0 p12 0 0 0 p123 p122 p121 p120 ff0ch 00h (output latch) r/w m = 0 to 3, 12; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note 38-pin products only caution for the 30-pin products, be sure to set bits 3 and 4 of p2, bits 0 to 5 of p3 to ?0?. chapter 4 port functions user?s manual u18685ej3v0ud 83 (3) pull-up resistor option re gisters (pu0 to pu2, pu3 note , and pu12) these registers specify whet her the on-chip pull-up resistors of p00 to p07, p10 to p17, p20 to p22, p23 note , p24 note , p25 to p27, p30 to p35 note , p120, and p123 are to be used or not. on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on- chip pull-up resistor has been specified in pu0, pu1, pu3 note , and pu12. on-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output pi ns, regardless of the settings of pu0, pu1, pu3 note , and pu12. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to 00h (08h for pu12). note 38-pin products only figure 4-17. format of pull-up resistor option register 7 pu07 symbol pu0 6 pu06 5 pu05 4 pu04 3 pu03 2 pu02 1 pu01 0 pu00 address ff30h after reset 00h r/w r/w pu17 pu1 pu16 pu15 pu14 pu13 pu12 pu11 pu10 ff31h 00h r/w 0 pu2 0 pu35 note pu34 note pu33 note pu32 note pu31 note pu30 note ff32h 00h r/w 0 pu3 note 0 0 0 pu123 0 0 pu120 ff33h 00h r/w pu12 ff3ch 08h r/w pu27 pu26 pu25 pu24 note pu23 note pu22 pu21 pu20 pumn pmn pin on-chip pull-up resistor selection (m = 0 to 3, 12; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected note 38-pin products only caution for the 30-pin products, be sure to set bits 3 and 4 of pu 2, bits 0 to 5 of pu3 to ?0?. chapter 4 port functions user?s manual u18685ej3v0ud 84 (4) port output mode resistors (pom0 to pom2, pom3 note , and pom12) these registers set the output mode of p00 to p07, p10 to p17, p20 to p22, p23 note , p24 note , p25 to p27, p30 to p35 note , p120 to p122. these registers can be set by a 1-bit or 8-bit memory mani pulation instruction. reset signal generation sets these registers to 00h. note 38-pin products only figure 4-18. format of pull-up resistor option register 7 pom07 symbol pom0 6 pom06 5 pom05 4 pom04 3 pom03 2 pom02 1 pom01 0 pom00 address ff38h after reset 00h r/w r/w pom17 pom1 pom16 pom15 pom14 pom13 pom12 pom11 pom10 ff39h 00h r/w 0 pom2 0 pom35 note pom34 note pom33 note pom32 note pom31 note pom30 note ff3ah 00h r/w 0 pom3 note 0 0 0 0 pom122 pom121 pom120 ff3bh 00h r/w pom12 ff3eh 00h r/w pom27 pom26 pom25 pom24 note pom23 note pom22 pom21 pom20 pommn pmn pin output mode selection (m = 0 to 3, 12; n = 0 to 7) 0 cmos output 1 n-ch open-drain output (p07:p-ch open-drain output) note 38-pin products only caution for the 30-pin products, be sure to set bits 3 and 4 of pom2, bits 0 to 5 of pom3 to ?0?. (5) reset pin mode register (rstmask) rstmask is the register that contro ls whether the alternate function ot her than the reset function of reset/p123/kr8/intp5 pin is enabled or disabled. this register can be set by a 1-bit or 8-bit memory mani pulation instruction. reset signal generation sets these registers to 00h. figure 4-19. format of reset pin mode register (rstmask) address: ff2eh after reset: 00h r/w symbol 7 6 5 4 <3> 2 1 0 rstmask 0 0 0 0 rstm 0 0 0 rstm controlling the alternate function other than the reset function is enabled or disabled 0 the alternate function is disabled. (reset /p123/kr8/intp5 pin functions as reset pin.) 1 the alternate function is enabled. (reset/p123/kr8/intp5 pin does not function as reset pin.) chapter 4 port functions user?s manual u18685ej3v0ud 85 4.4 port function operations port operations differ depending on whether the inpu t or output mode is set, as shown below. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruct ion, and the output latch content s are output from the pin. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. 4.4.2 reading from i/o port (1) output mode the output latch contents ar e read by a transfer instruction. t he output latch content s do not change. (2) input mode the pin status is read by a transfer instruct ion. the output latch c ontents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is wr itten to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode the pin level is read and an operation is performed on its cont ents. the result of the op eration is written to the output latch, but since the output buffer is off, the pin status does not change. the data of the output latch is clear ed when a reset signal is generated. chapter 4 port functions user?s manual u18685ej3v0ud 86 4.5 settings of port mode register, output latc h, pull-up resistor option register, and port output mode register when using alternate function to use the alternate function of a por t pin, set the port mode register, output latch, pull-up resistor option register, and port output mode register as shown in table 4-3. table 4-3. settings of port mode register, output la tch , pull-up resistor option register, and port output mode register when using alternate function alternate function pin name function name i/o pm p pu pom ti51 input 1 p00 to51 output 0 0 p01 toh0 output 0 0 ti000 input 1 p02 txd6 output 0 1 ti010 input 1 to00 output 0 0 p03 rxd6 input 1 p04 intp3 input 1 p05 intp2 input 1 ti50 input 1 to50 output 0 0 p06 intp1 input 1 rem output 0 0 1 p07 toh1 output 0 0 0 p10 to p17 kr0 to kr7 input 1 1 p27 intp4 input 1 p30 to p35 note kr9 to kr14 note input 1 1 exlvi input 1 p120 intp0 input 1 p121 x1 ? 0 x2 ? 0 p122 exclk input 1 reset input ? kr8 input ? 1 p123 intp5 input ? note 38-pin products only remark 1. : don?t care pm : port mode register p : port output latch pu : pull-up resistor option register pom : port output mode register 2. the p04/intp3, p05/intp2, p121/x1, and p122/x2/ exclk pins can be used as on-chip debug mode setting pins (ocd1a, ocd1b, ocd0a, ocd0b) when the on-chip debug function is used. for how to chapter 4 port functions user?s manual u18685ej3v0ud 87 connect an on-chip debug emulator with programming function (qb-mini2), see chapter 19 on-chip debug function . 4.6 cautions on 1-bit manipulation in struction for port register n (pn) when a 1-bit manipulation instruction is executed on a por t that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. user?s manual u18685ej3v0ud 88 chapter 5 clock generator 5.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following three kinds of system clo cks and clock oscillators are selectable. (1) main system clock <1> x1 oscillator this circuit oscillates a clock of f x = 1 to 4 mhz by connecting a resonator to x1 and x2. oscillation can be stopped by executing the stop inst ruction or using the main osc control register (moc). <2> internal high-speed oscillator this circuit oscillates a clock of f rh = 4 mhz 2 %. after a reset release, the cpu always starts operating with this internal high-speed oscillation clock. oscillation can be stopped by executing the stop instruction or using the internal oscillation mode register (rcm). an external main system clock (f exclk = 1 to 4 mhz) can also be supplied from the exclk/x2/p122 pin. an external main system clock input can be disabled by executing the stop in struction or using rcm. as the main system clock, a high-spee d system clock (x1 clock or external ma in system clock) or internal high- speed oscillation clock can be selected by using the main clock mode register (mcm). (2) internal low-speed oscillation clock (clock for watchdog timer) ? internal low-speed oscillator this circuit oscillates a clock of f rl = 240 khz (typ.). after a reset releas e, the internal low-speed oscillation clock always starts operating. oscillation can be stopped by using the internal oscill ation mode register (rcm) when ?internal low-speed oscillator can be stopped by software? is set by option byte. the internal low-speed oscillation clock cannot be us ed as the cpu clock. the following hardware operates with the internal low-speed oscillation clock. ? watchdog timer ? tmh1 (when f rl or f rl /2 7 is selected) remarks 1. f x : x1 clock oscillation frequency 2. f rh : internal high-speed oscillation clock frequency 3. f exclk : external main system clock frequency 4. f rl : internal low-speed oscillation clock frequency chapter 5 clock generator user?s manual u18685ej3v0ud 89 5.2 configuration of clock generator the clock generator includes the following hardware. table 5-1. configuration of clock generator item configuration control registers clock operation mode select register (oscctl) processor clock control register (pcc) internal oscillation mode register (rcm) main osc control register (moc) main clock mode register (mcm) oscillation stabilization time counter status register (ostc) oscillation stabilization time select register (osts) oscillators x1 oscillator internal high-speed oscillator internal low-speed oscillator chapter 5 clock generator user?s manual u18685ej3v0ud 90 figure 5-1. block diag ram of clock generator option byte 1: cannot be stopped 0: can be stopped internal oscillation mode register (rcm) lsrstop rsts rstop internal high- speed oscillator (4 mhz 2%) internal low- speed oscillator (240 khz (typ.)) f rl peripheral hardware clock (f prs ) watchdog timer, 8-bit timer h1 cpu clock (f cpu ) processor clock control register (pcc) pcc2 pcc1 pcc0 prescaler main system clock switch f xp peripheral hardware clock switch x1 oscillation stabilization time counter osts1 osts0 osts2 oscillation stabilization time select register (osts) 3 most 16 most 15 most 14 most 13 most 11 oscillation stabilization time counter status register (ostc) controller mcm0 xsel mcs mstop exclk oscsel clock operation mode select register (oscctl) 3 f xp 2 f xp 2 2 f xp 2 3 f xp 2 4 main clock mode register (mcm) main clock mode register (mcm) main osc control register (moc) f rh internal bus internal bus high-speed system clock oscillator crystal/ceramic oscillation external input clock x1/p121 x2/exclk/ p122 f xh f x f exclk selector stop + ? chapter 5 clock generator user?s manual u18685ej3v0ud 91 remarks 1. f x : x1 clock oscillation frequency 2. f rh : internal high-speed oscillation clock frequency 3. f exclk : external main system clock frequency 4. f xh : high-speed system clock frequency 5. f xp : main system clock frequency 6. f prs : peripheral hardware clock frequency 7. f cpu : cpu clock frequency 8. f rl : internal low-speed oscillation clock frequency 5.3 registers controlling clock generator the following seven registers are used to control the clock generator. ? clock operation mode sele ct register (oscctl) ? processor clock control register (pcc) ? internal oscillation mode register (rcm) ? main osc control register (moc) ? main clock mode register (mcm) ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) chapter 5 clock generator user?s manual u18685ej3v0ud 92 (1) clock operation mode select register (oscctl) this register selects the operati on modes of the high-speed system, and t he gain of the on-chip oscillator. oscctl can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 5-2. format of clock operati on mode select register (oscctl) address: ff9fh after reset: 00h r/w symbol <7> <6> 5 4 3 2 1 0 oscctl exclk oscsel 0 0 0 0 0 0 exclk oscsel high-speed system clock pin operation mode p121/x1 pin p122/x2/exclk pin 0 0 i/o port mode i/o port 0 1 x1 oscillation mode crystal/ceramic resonator connection 1 0 i/o port mode i/o port 1 1 external clock input mode i/o port external clock input caution to change the value of exclk and oscsel, be sure to confirm that bit 7 (mstop) of the main osc control register (moc) is 1 (the x1 oscillator stops or the external clock from the exclk pin is disabled). remark f xh : high-speed system clock frequency chapter 5 clock generator user?s manual u18685ej3v0ud 93 (2) processor clock control register (pcc) this register is used to select t he cpu clock, and the division ratio. pcc is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pcc to 01h. figure 5-3. format of processor clock control register (pcc) address: fffbh after reset: 01h r/w note symbol 7 6 5 4 3 2 1 0 pcc 0 0 0 0 0 pcc2 pcc1 pcc0 note bit 5 is read-only. caution be sure to clea r bits 3 to 7 to ?0?. remark f xp : main system clock oscillation frequency the fastest instruction can be executed in 2 clocks of the cpu clock in the pd179f11x, 179f12x microcontrollers. therefore, the re lationship between the cpu clock (f cpu ) and the minimum instruction execution time is as shown in table 5-2. table 5-2. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 2/f cpu main system clock high-speed system clock note1 internal high-speed oscillation clock note1 cpu clock (f cpu ) at 4 mhz operation at 4 mhz 2 % operation f xp 0.5 s note2 0.5 s (typ.) note2 f xp /2 1 s 1 s (typ.) f xp /2 2 2 s 2 s (typ.) f xp /2 3 4 s 4 s (typ.) f xp /2 4 8 s 8 s (typ.) notes 1. the main clock mode register (mcm) is used to set the main system clock supplied to cpu clock (high- speed system clock/internal high- speed oscillation clock) (see figure 5-6 ). 2. it is settable only when v dd = 2.0 to 3.6 v. cpu clock (f cpu ) selection pcc2 pcc1 pcc0 flmd0 = 0 flmd0 = 1 0 0 0 f xp f rh 0 0 1 f xp /2 (default) f rh /2 (default) 0 1 0 f xp /2 2 f rh /2 2 0 1 1 f xp /2 3 f rh /2 3 1 0 0 f xp /2 4 f rh /2 4 other than above setting prohibited chapter 5 clock generator user?s manual u18685ej3v0ud 94 (3) internal oscillation mode register (rcm) this register sets the operation mode of internal oscillator. rcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 80h note 1 . figure 5-4. format of internal oscillation mode register (rcm) address: ffa0h after reset: 80h note 1 r/w note 2 symbol <7> 6 5 4 3 2 <1> <0> rcm rsts 0 0 0 0 0 lsrstop rstop rsts status of internal high-speed oscillator 0 waiting for accuracy stabilizati on of internal high-speed oscillator 1 stability operating of internal high-speed oscillator lsrstop internal low-speed oscillator oscillating/stopped 0 internal low-speed oscillator oscillating 1 internal low-s peed oscillator stopped rstop internal high-speed oscillator oscillating/stopped 0 internal high-spe ed oscillator oscillating 1 internal high-speed oscillator stopped notes 1. the value of this register is 00h immedi ately after a reset release but automatically changes to 80h after internal high-speed oscillator has been stabilized. 2. bit 7 is read-only. caution when setting rstop to 1, be sure to confirm that the cpu operates with a clock other than the internal high -speed oscillation clock. sp ecifically, set under either of the following conditions. ? when mcs = 1 (when cpu operates with the high-speed system clock) in addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock before setting rstop to 1. chapter 5 clock generator user?s manual u18685ej3v0ud 95 (4) main osc control register (moc) this register selects the operati on mode of the high-speed system clock. this register is used to stop the x1 oscillator or to disable an external clock input from the exclk pin when the cpu operates with a clock other than the high-speed system clock. moc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 80h. figure 5-5. format of main osc control register (moc) address: ffa2h after reset: 80h r/w symbol <7> 6 5 4 3 2 1 0 moc mstop 0 0 0 0 0 0 0 control of high-speed system clock operation mstop x1 oscillation mode external clock input mode 0 x1 oscillator operating external clock from exclk pin is enabled 1 x1 oscillator stopped external clock from exclk pin is disabled cautions 1. when setting ms top to 1, be sure to confirm that the cpu operates with a clock other than the high-speed system clock. specifically , set under either of the following conditions. ? when mcs = 0 (when cpu operates with the internal high-speed oscillation clock) 2. do not clear mstop to 0 while bit 6 (oscsel) of the clock operation mode select register (oscctl) is 0 (i/o port mode). 3. the peripheral hardware cannot operate when the pe ripheral hardware clock is stopped. to resume the operation of the peripheral hardware after the peripheral hardware clock has been stopped, in itialize the peri pheral hardware. chapter 5 clock generator user?s manual u18685ej3v0ud 96 (5) main clock mode register (mcm) this register selects the main system clock supplied to cpu clock and clock supplied to peripheral hardware clock. mcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 5-6. format of main clock mode register (mcm) address: ffa1h after reset: 00h r/w note symbol 7 6 5 4 3 <2> <1> <0> mcm 0 0 0 0 0 xsel mcs mcm0 selection of clock supplied to main system clock and peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 0 0 0 1 internal high-speed oscillation clock (f rh ) 1 0 internal high-speed oscillation clock (f rh ) 1 1 high-speed system clock (f xh ) high-speed system clock (f xh ) mcs main system clock status 0 operates with internal high-speed oscillation clock 1 operates with hi gh-speed system clock note bit 1 is read-only. cautions 1. xsel can be change d only once after a reset release. 2. a clock other than f prs is supplied to the following peripheral functions regardless of the se tting of xsel and mcm0. ? watchdog timer (operates with intern al low-speed oscillation clock) ? when ?f rl ? or ?f rl /2 7 ? is selected as the count clock for 8-bit timer h1 (operates with internal low-speed oscillation clock) ? peripheral hardware selects the ext ernal clock as the clock source (except when the external count clock of tm00 is selected (ti000 pin valid edge)) chapter 5 clock generator user?s manual u18685ej3v0ud 97 (6) oscillation stabilization time c ounter status register (ostc) this is the register that indicates t he count status of the x1 clock oscillati on stabilization time counter. when x1 clock oscillation starts with the internal high-speed o scillation clock used as the cpu clock, the x1 clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lv i, and wdt), the stop instruction and mstop (bit 7 of moc register) = 1 clear ostc to 00h. figure 5-7. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status f x = 1 mhz f x = 2 mhz f x = 4 mhz 0 0 0 0 0 less than 2 11 /f x less than 2.04 ms less than 1.02 ms less than 510 s 1 0 0 0 0 2 11 /f x min. 2.04 ms min 1.02 ms min 510 s min 1 1 0 0 0 2 13 /f x min. 8.20 ms min 4.10 ms min 2.04 ms min 1 1 1 0 0 2 14 /f x min. 16.38 ms min. 8.19 ms min. 4.10 ms min 1 1 1 1 0 2 15 /f x min. 32.77 ms min. 16.38 ms min. 8.19 ms min. 1 1 1 1 1 2 16 /f x min. 65.45 ms min. 32.77 ms min. 16.38 ms min. cautions 1. after the above time has elapsed, th e bits are set to 1 in order from most11 and remain 1. 2. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 3. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 5 clock generator user?s manual u18685ej3v0ud 98 (7) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the operation waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confirm with ostc that the desired oscillation stabilization time has elapsed after the stop mode is released. the oscillation stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 05h. figure 5-8. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection f x = 1 mhz f x = 2 mhz f x = 4 mhz 0 0 1 2 11 /f x 2.04 ms 1.02 ms 510 s 0 1 0 2 13 /f x 8.19 ms 4.10 ms 2.04 m 0 1 1 2 14 /f x 16.38 ms 8.19 ms 4.10 ms 1 0 0 2 15 /f x 32.77 ms 16.38 ms 8.19 ms 1 0 1 2 16 /f x 65.45 ms 32.77 ms 16.38 ms other than above setting prohibited cautions 1. to set the stop mode when the x1 clock is used as the cpu clock, set osts before executing the stop instruction. 2. do not change the value of the osts register during the x1 clock oscillation stabilization time. 3. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 4. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 5 clock generator user?s manual u18685ej3v0ud 99 5.4 system clock oscillator 5.4.1 x1 oscillator the x1 oscillator oscillates with a cr ystal resonator or ceramic resonator (1 to 4 mhz) connected to the x1 and x2 pins. an external clock can also be input. in this case, input the clock signal to the exclk pin. figure 5-9 shows an example of the exte rnal circuit of the x1 oscillator. figure 5-9. example of extern al circuit of x1 oscillator (a) crystal or ceramic osc illation (b) external clock v ss x1 x2 crystal resonator or ceramic resonator exclk external clock caution when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring leng th as short as possible. do not cross the wiring wi th the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the o scillator capacitor th e same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. cautions are listed on the figure 5-10. figure 5-10. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line x2 v ss x1 x1 v ss x2 port chapter 5 clock generator user?s manual u18685ej3v0ud 100 figure 5-10. examples of incorr ect resonator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (e) signals are fetched v ss x1 x2 5.4.2 internal hi gh-speed oscillator the internal high-speed oscillat or is incorporated in the pd179f11x, 179f12x microcontrollers. oscillation can be controlled by the internal oscillation mode register (rcm). after a reset release, the internal high-speed o scillator automatically starts oscillation (4 mhz 2 %). 5.4.3 internal low-speed oscillator the internal low-speed oscillator is incorporated in the pd179f11x, 179f12x microcontrollers. the internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer h1. the internal low-speed oscillation clock cannot be used as the cpu clock. ?can be stopped by software? or ?cannot be stopped? ca n be selected by the option byte. when ?can be stopped by software? is set, oscillation can be controlled by the internal oscillation mode register (rcm). chapter 5 clock generator user?s manual u18685ej3v0ud 101 after a reset release, the internal low-speed oscillator automatically starts oscillati on, and the watchdog timer is driven (240 khz (typ.)) if the watchdog timer operation is enabled using the option byte. 5.4.4 prescaler the prescaler generates various clocks by dividing the main system clock when the ma in system clock is selected as the clock to be supplied to the cpu. 5.5 clock generator operation the clock generator generates the following clocks and contro ls the operation modes of the cpu, such as standby mode (see figure 5-1 ). ? main system clock f xp ? high-speed system clock f xh x1 clock f x external main system clock f exclk ? internal high-speed oscillation clock f rh ? internal low-speed oscillation clock f rl ? cpu clock f cpu ? peripheral hardware clock f prs the cpu starts operation when the internal high-speed osc illator starts outputting after a reset release in the pd179f11x, 179f12x microcontroller s, thus enabling the following. (1) enhancement of security function when the x1 clock is set as the cpu clock by the defaul t setting, the device cannot operate if the x1 clock is damaged or badly connected and therefore does not operate after reset is released. however, the start clock of the cpu is the internal high-speed oscillation clock, so the device can be started by the internal high-speed oscillation clock after a reset release. consequently , the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. (2) improvement of performance because the cpu can be started with out waiting for the x1 clock oscillation stabilization time, the total performance can be improved. when the power supply voltage is turned on, the cl ock generator operation is shown in figure 5-11. chapter 5 clock generator user?s manual u18685ej3v0ud 102 figure 5-11. clock generator operation wh en power supply voltage is turned on internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software x1 clock oscillation stabilization time: 2 11 /f x to 2 16 /f x note 2 starting x1 oscillation is set by software. reset processing (60 to 160 s) <3> waiting for voltage stabilization internal reset signal 0 v 1.8 v (typ.) power supply voltage (v dd ) <1> <2> <4> <5> note 1 (1.96 to 5.4 ms) <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 1.8 v (typ.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> the cpu starts operation on the inte rnal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage of the power supply and regulator have elapsed, and then reset processing is performed. <4> set the start of oscillation of the x1 clock via software (see (1) in 5.6.1 example of controlling high-speed system clock) . <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 5.6.1 example of controlling high-speed system clock ). notes 1. the internal voltage stabilization time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 2. when releasing a reset (above figure) or releas ing stop mode while the cpu is operating on the internal high-speed oscillation clock, confirm the osci llation stabilization time for the x1 clock using the oscillation stabilization time count er status register (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation st abilization time when releasing stop mode using the oscillation stabilization time select register (osts). caution it is not necessary to wait for the oscillation stabilization time when an externa l clock input from the exclk pin is used. remark while the microcontroller is operating, a clock t hat is not used as the cpu clock can be stopped via software settings. the internal high-speed o scillation clock and high-speed system clock can be stopped by executing the stop instruction (see (4) in 5.6.1 example of co ntrolling high-speed system clock , and (3) in 5.6.2 example of controlling inte rnal high-speed oscillation clock ). chapter 5 clock generator user?s manual u18685ej3v0ud 103 5.6 controlling clock 5.6.1 example of control ling high-speed system clock the following two types of high-s peed system clocks are available. ? x1 clock: crystal/ceramic resonator is connected across the x1 and x2 pins. ? external main system clock: exter nal clock is input to the exclk pin. when the high-speed system clock is not used, the x1/p 121 and x2/exclk/p122 pins can be used as i/o port pins. caution the x1/p121 and x2/exclk/p122 pins are in the i/o port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating x1 clock (2) when using external main system clock (3) when using high-speed system clock as cpu clock and peripheral hardware clock (4) when stopping high-speed system clock (1) example of setting procedure when oscillating the x1 clock <1> setting p121/x1/ocd0a and p122/x2/exclk/ocd0b pi ns and selecting x1 clock or external clock (oscctl register) when exclk is cleared to 0 and oscsel is set to 1, the mode is switched from port mode to x1 oscillation mode. exclk oscsel operation mode of high- speed system clock pin p121/x1 pin p122/x2/exclk pin 0 1 x1 oscillation mode crystal/ceramic resonator connection <2> controlling oscillation of x1 clock (moc register) if mstop is cleared to 0, the x1 oscillator starts oscillating. <3> waiting for the stabilization of the oscillation of x1 clock check the ostc register and wait for the necessary time. during the wait time, other software processing c an be executed with the internal high-speed oscillation clock. cautions 1. do not change the value of exclk and oscsel while the x1 clock is operating. 2. set the x1 clock after th e supply voltage has r eached the operable volt age of the clock to be used (see chapter 21 el ectrical specifications). (2) example of setting procedure when using the external main system clock <1> setting p121/x1/ocd0a and p122/x2/exclk/ocd0b pins and selecting operation mode (oscctl register) when exclk and oscsel are set to 1, the mode is switched from port mode to external clock input mode. exclk oscsel operation mode of high- speed system clock pin p121/x1 pin p122/x2/exclk pin 1 1 external clock input mode i/o port external clock input chapter 5 clock generator user?s manual u18685ej3v0ud 104 <2> controlling external main system clock input (moc register) when mstop is cleared to 0, the input of the external main system clock is enabled. cautions 1. do not change the value of exclk a nd oscsel while the external main system clock is operating. 2. set the external main system clock afte r the supply voltage h as reached the operable voltage of the clock to be used ( see chapter 21 electrical specifications). (3) example of setting procedure when using high-speed system clo ck as cpu clock and peripheral hardware clock <1> setting high-speed system clock oscillation note (see 5.6.1 (1) example of setting proce dure when oscillating the x1 clock and (2) example of setting procedure when using th e external main system clock. ) note the setting of <1> is not necessary when hi gh-speed system clock is already operating. <2> setting the high-speed system clock as the main system clock (mcm register) when xsel and mcm0 are set to 1, the high-speed syst em clock is supplied as the main system clock and peripheral hardware clock. selection of main system clock and clock supplied to peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 1 1 high-speed system clock (f xh ) high-speed system clock (f xh ) caution if the high-speed system clock is selected as the main syst em clock, a clock other than the high-speed system clock cannot be set as the peripheral hardware clock. <3> setting the main system clock as the cpu clo ck and selecting the division ratio (pcc register) when css is cleared to 0, the main system clock is supplied to the cpu. to select the cpu clock division ratio, use pcc0, pcc1, and pcc2. cpu clock (f cpu ) selection pcc2 pcc1 pcc0 flmd0 = 0 flmd0 = 1 0 0 0 f xp f rh 0 0 1 f xp /2 (default) f rh /2 (default) 0 1 0 f xp /2 2 f rh /2 2 0 1 1 f xp /2 3 f rh /2 3 1 0 0 f xp /2 4 f rh /2 4 other than above setting prohibited (4) example of setting procedure when stopping the high-speed system clock the high-speed system clock can be st opped in the foll owing two ways. ? executing the stop instruction and stopping the x1 oscillation (disabling clock input if the external clock is used) ? setting mstop to 1 and stopping the x1 oscillation (dis abling clock input if the external clock is used) (a) to execute a stop instruction <1> setting to stop peripheral hardware chapter 5 clock generator user?s manual u18685ej3v0ud 105 stop peripheral hardware that c annot be used in the stop mode (f or peripheral hardware that cannot be used in stop mode, see chapter 13 standby function ). <2> setting the x1 clock oscillation st abilization time after standby release when the cpu is operating on the x1 clock, set t he value of the osts r egister before the stop instruction is executed. <3> executing the stop instruction when the stop instruction is ex ecuted, the system is placed in the stop mode and x1 oscillation is stopped (the input of the ex ternal clock is disabled). (b) to stop x1 oscillation (disabling exter nal clock input) by setting mstop to 1 <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with mcs that the cpu is operating on a clock other t han the high-speed system clock. when mcs = 1, the high-speed system clock is supp lied to the cpu, so change the cpu clock to the internal high-speed oscillation clock. mcs cpu clock status 0 internal high-speed oscillation clock 1 high-speed system clock <2> stopping the high-speed system clock (moc register) when mstop is set to 1, x1 oscillation is stopp ed (the input of the external clock is disabled). caution be sure to confirm that mcs = 0 when setting mstop to 1. in addition, stop peripheral hardware that is operating on the high-speed system clock. 5.6.2 example of controlling inte rnal high-speed oscillation clock the following describes examples of clock setting procedures for the following cases. (1) when restarting oscillation of the internal high-speed oscillation clock (2) when using internal high-speed oscillation clock as cpu clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock (3) when stopping the internal high-speed oscillation clock (1) example of setting procedure wh en restarting oscillation of the in ternal high-speed oscillation clock note 1 <1> setting restart of oscillation of the intern al high-speed oscillation clock (rcm register) when rstop is cleared to 0, the internal high-speed oscillation clock starts operating. <2> waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (rcm register) wait until rsts is set to 1 note 2 . notes 1. after a reset release, the internal high-speed oscillator automatically starts oscillating and the internal high-speed oscillation clock is selected as the cpu clock. 2. this wait time is not necessary if high accura cy is not necessary for the cpu clock and peripheral hardware clock. chapter 5 clock generator user?s manual u18685ej3v0ud 106 (2) example of setting procedure when using intern al high-speed oscillation clock as cpu clock, and internal high-speed oscillation clock or high-speed system clo ck as peripheral hardware clock <1> ? restarting oscillation of the internal high-speed oscillation clock note (see 5.6.2 (1) example of setting procedure when restarting oscillation of the internal high- speed oscillation clock ). ? oscillating the high-speed system clock note (this setting is required when using the high-speed system clock as the peripheral hardware clock. see 5.6.1 (1) example of setting proced ure when oscillating the x1 clock and (2) example of setting procedure when using th e external main system clock. ) note the setting of <1> is not necessary when the internal high-speed oscillation clock or high- speed system clock is already operating. <2> selecting the clock s upplied as the main system clock and peri pheral hardware clock (mcm register) set the main system clock and peripheral hardware clock using xsel and mcm0. selection of main system clock and clock supplied to peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 0 0 0 1 internal high-speed oscillation clock (f rh ) 1 0 internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) <3> selecting the cpu clock division ratio (pcc register) when css is cleared to 0, the main system clock is supplied to the cpu. to select the cpu clock division ratio, use pcc0, pcc1, and pcc2. cpu clock (f cpu ) selection pcc2 pcc1 pcc0 flmd0 = 0 flmd0 = 1 0 0 0 f xp f rh 0 0 1 f xp /2 (default) f rh /2 (default) 0 1 0 f xp /2 2 f rh /2 2 0 1 1 f xp /2 3 f rh /2 3 1 0 0 f xp /2 4 f rh /2 4 other than above setting prohibited (3) example of setting procedure when stoppi ng the internal high-speed oscillation clock the internal high-speed oscillation clock can be stopped in the following two ways. ? executing the stop instruction to set the stop mode ? setting rstop to 1 and stopping the internal high-speed oscillation clock (a) to execute a stop instruction <1> setting of peripheral hardware stop peripheral hardware that c annot be used in the stop mode (f or peripheral hardware that cannot be used in stop mode, see chapter 13 standby function ). <2> setting the x1 clock oscillation st abilization time after standby release when the cpu is operating on the x1 clock, set t he value of the osts r egister before the stop instruction is executed. chapter 5 clock generator user?s manual u18685ej3v0ud 107 <3> executing the stop instruction when the stop instruction is ex ecuted, the system is placed in the stop mode and internal high- speed oscillation clock is stopped. (b) to stop internal high-speed o scillation clock by setting rstop to 1 <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with mcs that the cpu is operating on a clock other than the internal high-speed oscillation clock. when mcs = 0, the internal high-speed oscillation cl ock is supplied to the cpu, so change the cpu clock to the high-speed system clock. mcs cpu clock status 0 internal high-speed oscillation clock 1 high-speed system clock <2> stopping the internal high-speed oscillation clock (rcm register) when rstop is set to 1, internal high-speed oscillation clock is stopped. caution be sure to confirm that mcs = 1 when setting rstop to 1. in addition, stop peripheral hardware that is operating on the in ternal high-speed oscillation clock. 5.6.3 example of controlling in ternal low-speed oscillation clock the internal low-speed oscillation clock cannot be used as the cpu clock. only the following peripheral hardware can operate with this clock. ? watchdog timer ? 8-bit timer h1 (if f rl is selected as the count clock) in addition, the following operation modes can be selected by the option byte. ? internal low-speed oscillator cannot be stopped ? internal low-speed oscillator can be stopped by software the internal low-speed oscillator autom atically starts oscillation after a reset release, and the watchdog timer is driven (240 khz (typ.)) if the watchdog timer operation has been enabled by the option byte. (1) example of setting procedure when stoppi ng the internal low-speed oscillation clock <1> setting lsrstop to 1 (rcm register) when lsrstop is set to 1, the internal low-speed oscillation clock is stopped. (2) example of setting procedure when restarting osc illation of the internal low-speed oscillation clock <1> clearing lsrstop to 0 (rcm register) when lsrstop is cleared to 0, the internal low-speed oscillation clock is restarted. caution if ?internal low-speed oscillator cannot be st opped? is selected by the option byte, oscillation of the internal low-speed oscillati on clock cannot be controlled. chapter 5 clock generator user?s manual u18685ej3v0ud 108 5.6.4 clocks supplied to cp u and peripheral hardware the following table shows the relation among the clocks supplied to the cpu and peripheral hardware, and setting of registers. table 5-3. clocks supplied to cpu and peripheral hardware, and register setting supplied clock clock supplied to cpu clock su pplied to peripheral hardware xsel mcm0 exclk internal high-speed oscillation clock 0 x1 clock 1 0 0 internal high-speed oscillation clock external main system clock 1 0 1 x1 clock 1 1 0 external main system clock 1 1 1 remarks 1. xsel: bit 2 of the main clock mode register (mcm) 2. mcm0: bit 0 of mcm 3. exclk: bit 7 of the clock operat ion mode select register (oscctl) 4. : don?t care chapter 5 clock generator user?s manual u18685ej3v0ud 109 5.6.5 cpu clock stat us transition diagram figure 5-12 shows the cpu clock status transition diagram of this product. figure 5-12. cpu clock stat us transition diagram power on reset release v dd 1.8v (typ.) v dd 1.8 v (min.) v dd < 1.8 v (typ.) internal low-speed oscillation: woken up internal high-speed oscillation: woken up x1 oscillation/exclk input: stops (i/o port mode) internal low-speed oscillation: operating internal high-speed oscillation: operating x1 oscillation/exclk input: stops (i/o port mode) cpu: operating with internal high- speed oscillation internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: selectable by cpu cpu: internal high- speed oscillation stop internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops cpu: internal high- speed oscillation halt internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: operable cpu: operating with x1 oscillation or exclk input cpu: x1 oscillation/exclk input stop cpu: x1 oscillation/exclk input halt internal low-speed oscillation: operable internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: operating internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops internal low-speed oscillation: operable internal high-speed oscillation: operable x1 oscillation/exclk input: operating (b) (a) (c) (d) (e) (f) (g) chapter 5 clock generator user?s manual u18685ej3v0ud 110 table 5-4 shows transition of the cpu clock and examples of setting the sfr registers. table 5-4. cpu clock transition a nd sfr register setting examples (1/2) (1) cpu operating with internal high-speed oscillation clock (b) a fter reset release (a) status transition sfr register setting (a) (b) sfr registers do not have to be se t (default status after reset release). (2) cpu operating with high-speed system clock (c) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) setting flag of sfr register status transition exclk oscsel mstop ostc register xsel mcm0 (a) (b) (c) (x1 clock: 1 mhz f xh 4 mhz) 0 1 0 must be checked 1 1 (a) (b) (c) (external main clock: 1 mhz f xh 4 mhz) 1 1 0 must not be checked 1 1 (3) cpu clock changing from inte rnal high-speed oscillation clock (b) to high-speed system clock (c) (setting sequence of sfr registers) setting flag of sfr register status transition exclk oscsel mstop ostc register xsel note mcm0 (b) (c) (x1 clock: 1 mhz f xh 4 mhz) 0 1 0 must be checked 1 1 (b) (c) (external main clock: 1 mhz f xh 4 mhz) 1 1 0 must not be checked 1 1 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-spe ed system clock note the value of this flag can be changed only once after a re set release. this setting is not necessary if it has already been set. caution set the clock after the supply voltage has reached the operable voltage of the clock to be set (see chapter 21 electrical specifications). remarks 1. (a) to (g) in table 5-4 correspond to (a) to (g) in figure 5-12. 2. exclk, oscsel: bits 7 and 6 of the clock operation mode select register (oscctl) mstop: bit 7 of the ma in osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) : don?t care chapter 5 clock generator user?s manual u18685ej3v0ud 111 table 5-4. cpu clock transition a nd sfr register setting examples (2/2) (4) cpu clock changing from high- speed system clock (c) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) setting flag of sfr register status transition rstop rsts mcm0 (c) (b) 0 confirm this flag is 1. 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock caution set the clock after the supply voltage has reached the operable voltage of the clock to be set (see chapter 21 electrical specifications. (5) halt mode (d) set while cpu is operating with internal high -speed oscillation clock (b), halt mode (e) set while cpu is ope rating with high-speed system clock (c) status transition setting (b) (d) (c) (e) executing halt instruction (6) stop mode (f) set while cpu is operating wit h internal high-speed oscillation clock (b), stop mode (g) set while cpu is ope rating with high-speed system clock (c) (setting sequence) status transition setting (b) (f) (c) (g) stopping peripheral functions that cannot operate in stop mode executing stop instruction remarks 1. (a) to (g) in table 5-4 correspond to (a) to (g) in figure 5-12. 2. mcm0: bit 0 of the main clock mode register (mcm) rsts, rstop: bits 7 and 0 of the internal oscillation mode register (rcm) chapter 5 clock generator user?s manual u18685ej3v0ud 112 5.6.6 condition before changing cpu clo ck and processing after changing cpu clock condition before changing the cpu clock and processing after changing the cpu clock are shown below. table 5-5. changing cpu clock cpu clock before change after change condition before change processing after change x1 clock stabilization of x1 oscillation ? mstop = 0, oscsel = 1, exclk = 0 ? after elapse of oscillation stabilization time internal high-speed oscillator can be stopped (rstop = 1). internal high- speed oscillation clock external main system clock enabling input of exter nal clock from exclk pin ? mstop = 0, oscsel = 1, exclk = 1 internal high-speed oscillator can be stopped (rstop = 1). x1 clock x1 oscillation can be stopped (mstop = 1). external main system clock internal high- speed oscillation clock oscillation of internal high-speed oscillator ? rstop = 0 external main system clock input can be disabled (mstop = 1). 5.6.7 time required for switchover of cpu clock and main system clock by setting bits 0 to 2 (pcc0 to pcc2) of the processor cl ock control register (pcc), the division ratio of the main system clock can be changed. the actual switchover operat ion is not performed immediately after rewr iting to pcc; operat ion continues on the pre-switchover clock for several clocks (see table 5-6 ). table 5-6. time required for switchover of cpu clock and main system cl ock cycle division factor set value before switchover set value after switchover pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 16 clocks 16 clocks 16 clocks 16 clocks 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks 1 0 0 1 clock 1 cloc k 1 clock 1 clock remark the number of clocks listed in table 5-6 is the number of cpu clocks before switchover. by setting bit 0 (mcm0) of the main clock mode register (mcm), the main system clo ck can be switch ed (between the internal high-speed oscillation clock and the high-speed system clock). the actual switchover oper ation is not performed immediately after re writing to mcm0; operation continues on the pre-switchover clock for several clocks (see table 5-7 ). whether the cpu is operating on the internal high-speed oscillation cloc k or the high-speed system clock can be ascertained using bit 1 (mcs) of mcm. chapter 5 clock generator user?s manual u18685ej3v0ud 113 table 5-7. maximum time required for main system clock switchover set value before switchover set value after switchover mcm0 mcm0 0 1 0 1 + 2f rh /f xh clock 1 1 + 2f xh /f rh clock caution when switching the intern al high-speed oscillation clock to the high-speed system clock, bit 2 (xsel) of mcm must be set to 1 in advance. the value of xsel can be changed only once after a reset release. remarks 1. the number of clocks listed in table 5-7 is t he number of main system clocks before switchover. 2. calculate the number of clocks in t able 5-7 by removing the decimal portion. example when switching the main system clock from the internal high-speed oscillation clock to the high-speed system clock (@ oscillation with f rh = 1 mhz, f xh = 4 mhz) 1 + 2f rh /f xh = 1 + 2 1/4 = 1 + 2 0.25 = 1 + 0.5 = 1.5 1 clock 5.6.8 conditions before cl ock oscillation is stopped the following lists the register flag settings for stopping th e clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. table 5-8. conditions before the clo ck oscillation is stopped and flag settings clock conditions before clock oscillation is stopped (external clock input disabled) flag settings of sfr register internal high-speed oscillation clock mcs = 1 (the cpu is operating on a clock ot her than the internal high-speed oscillation clock) rstop = 1 x1 clock external main system clock mcs = 0 (the cpu is operating on a clock other than the high-speed system clock) mstop = 1 chapter 5 clock generator user?s manual u18685ej3v0ud 114 5.6.9 peripheral hardware and source clocks the following lists peripheral hardware and source clocks incorporated in the pd179f11x, 179f12x microcontrollers. table 5-9. peripheral ha rdware and source clocks source clock peripheral hardware peripheral hardware clock (f prs ) internal low- speed oscillation clock (f rl ) tm50 output external clock from peripheral hardware pins 16-bit timer/ event counter 00 y n n y (ti000 pin) 50 y n n y (ti50 pin) 8-bit timer/ event counter 51 y n n y (ti51 pin) h0 y n y n 8-bit timer h1 y y n n watchdog timer n y n n clock output note 2 y n n n serial interface uart6 y n y n remark y: can be selected, n: cannot be selected user?s manual u18685ej3v0ud 115 chapter 6 16-bit timer/event counter 00 6.1 functions of 16-bit timer/event counter 00 16-bit timer/event counter 00 has the following functions. (1) interval timer 16-bit timer/event counter 00 generates an inte rrupt request at the preset time interval. (2) square-wave output 16-bit timer/event counter 00 can output a square wave with any selected frequency. (3) external event counter 16-bit timer/event counter 00 c an measure the number of pulses of an externally input signal. (4) one-shot pulse output 16-bit timer event counter 00 can output a one-shot pulse whose output pulse width can be set freely. (5) ppg output 16-bit timer/event counter 00 can output a rectangular wa ve whose frequency and output pulse width can be set freely. (6) pulse width measurement 16-bit timer/event counter 00 can measure the pulse width of an externally input signal. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 116 6.2 configuration of 16-bit timer/event counter 00 16-bit timer/event counter 00 includes the following hardware. table 6-1. configuration of 16-bit timer/event counter 00 item configuration time/counter 16-bit timer counter 00 (tm00) register 16-bit timer capture/compare registers 000, 010 (cr000, cr010) timer input ti000, ti010 pins timer output to00 pin, output controller control registers 16-bit timer mode control register 00 (tmc00) 16-bit timer capture/compare control register 00 (crc00) 16-bit timer output control register 00 (toc00) prescaler mode register 00 (prm00) port mode register 0 (pm0) port register 0 (p0) port output mode register 0 (pom0) figures 6-1 shows the block diagram. figure 6-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/to00/p03/ rxd6 f prs f prs /2 2 f prs /2 8 f prs ti000/p02/txd6 prescaler mode register 00 (prm00) 2 prm001 prm000 crc002 16-bit timer capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator crc002 crc001 crc000 inttm000 to00/ti010/ p03/rxd6 inttm010 to00 output 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit timer capture/compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller ospe00 ospt00 output latch (p03) to cr010 pom03 pm03 caution 1. the valid edge of ti010 and timer output (to00) cannot be used fo r the p03 pin at the same time. select either of the functions. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 117 cautions 2. if clearing of bits 3 and 2 (tmc003 a nd tmc002) of 16-bit timer mode control register 00 (tmc00) to 00 and input of the capture trigger c onflict, then the capture d data is undefined. 3. to change the mode from the capture mode to the comparison mode, first clear the tmc003 and tmc002 bits to 00, and then change the setting. a value that has been once captured remains stored in cr000 unless the device is reset. if the mode has been changed to the comparis on mode, be sure to set a comparison value. (1) 16-bit timer counter 00 (tm00) tm00 is a 16-bit read-only regist er that counts count pulses. the counter is incremented in synchronization with the rising edge of the count clock. if the count value is read during operat ion, then input of the count clock is temporarily stopped, and the count value at that point is read. figure 6-2. format of 16-bit timer counter 00 (tm00) tm00 ff11h ff10h address: ff10h, ff11h after reset: 0000h r 1514131211109876543210 the count value of tm00 can be read by reading tm00 when the value of bits 3 and 2 (tmc003 and tmc002) of 16-bit timer mode control register 00 (tmc00) is other th an 00. the value of tm00 is 0000h if it is read when tmc003 and tmc002 = 00. the count value is reset to 0000h in the following cases. ? at reset signal generation ? if tmc003 and tmc002 are cleared to 00 ? if the valid edge of the ti000 pin is input in the mode in which the clear & start occurs when inputting the valid edge to the ti000 pin ? if tm00 and cr000 match in the mode in which the clear & start occurs when tm00 and cr000 match ? ospt00 is set to 1 in one-shot pulse output m ode or the valid edge is input to the ti000 pin cautions 1. even if tm00 is read, the value is not captured by cr010. 2. if tm00 is referred to during a timer c ount, a timer count will be stopped durin g reference processing, and a timer count is resumed after reference processing is finished. therefore, if processing which refe rs to tm00 is performed, an error will arise at a timer count. (2) 16-bit timer capture/compare regi ster 000 (cr000), 16-bit timer cap ture/compare register 010 (cr010) cr000 and cr010 are 16-bit registers that are used with a capture function or compar ison function selected by using crc00. change the value of cr000 while the timer is stopped (tmc003 and tmc002 = 00). the value of cr010 can be changed during operation if the val ue has been set in a specific way. for details, see 6.5.1 rewriting cr010 during tm00 operation . these registers can be read or written in 16-bit units. reset signal generation sets these registers to 0000h. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 118 figure 6-3. format of 16-bit timer ca pture/compare register 000 (cr000) cr000 ff13h ff12h address: ff12h, ff13h after reset: 0000h r/w 1514131211109876543210 (i) when cr000 is used as a compare register the value set in cr000 is constantly compared with the tm00 count value, and an interrupt request signal (inttm000) is generated if they match. t he value is held until cr000 is rewritten. caution cr000 does not perform the capture operati on when it is set in the comparison mode, even if a capture trigger is input to it. (ii) when cr000 is used as a capture register the count value of tm00 is captured to cr000 when a capture trigger is input. as the capture trigger, an edge of a phas e reverse to that of the ti000 pin or the valid edge of the ti010 pin can be selected by using crc00 or prm00. figure 6-4. format of 16-bit timer ca pture/compare register 010 (cr010) cr010 ff15h ff14h address: ff14h, ff15h after reset: 0000h r/w 1514131211109876543210 (i) when cr010 is used as a compare register the value set in cr010 is constantly compared with the tm00 count value, and an interrupt request signal (inttm010) is generated if they match. caution cr010 does not perform the capture operati on when it is set in the comparison mode, even if a capture trigger is input to it. (ii) when cr010 is used as a capture register the count value of tm00 is captured to cr010 when a capture trigger is input. it is possible to select the valid edge of the ti000 pin as the capture trigger. the ti000 pin valid edge is set by prm00. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 119 (iii) setting range when cr000 or cr 010 is used as a compare register when cr000 or cr010 is used as a compare register, set it as shown below. operation cr000 register setting range cr010 register setting range operation as interval timer operation as square-wave output operation as external event counter 0000h < n ffffh 0000h note m ffffh normally, this setting is not used. mask the match interrupt signal (inttm010). operation in the clear & start mode entered by ti000 pin valid edge input operation as free-running timer 0000h note n ffffh 0000h note m ffffh operation as ppg output m < n ffffh 0000h note m < n operation as one-shot pulse output 0000h note n ffffh (n m) 0000h note m ffffh (m n) note when 0000h is set, a match interrupt immediately after the timer operation does not occur and timer output is not changed, and the first match timing is as follows . a match interrupt occurs at the timing when the timer counter (tm00 register) is changed from 0000h to 0001h. ? when the timer counter is cleared due to overflow ? when the timer counter is cleared due to ti000 pin valid edge (when clear & start mode is entered by ti000 pin valid edge input) ? when the timer counter is cleared due to compare ma tch (when clear & start mode is entered by match between tm00 and cr000 (cr000 = other than 0000h, cr010 = 0000h)) operation enabled (other than 00) tm00 register timer counter clear interrupt signal is not generated interrupt signal is generated timer operation enable bit (tmc003, tmc002) interrupt request signal compare register set value (0000h) operation disabled (00) remarks 1. n: cr000 register set value, m: cr010 register set value 2. for details of tmc003 and tmc002, see 6.3 (1) 16-bit timer mode control register 00 (tmc00) . chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 120 table 6-2. capture operation of cr000 and cr010 external input signal capture operation ti000 pin input ti010 pin input set values of es001 and es000 position of edge to be captured set values of es101 and es100 position of edge to be captured 01: rising 01: rising 00: falling 00: falling crc001 = 1 ti000 pin input (reverse phase) 11: both edges (cannot be captured) crc001 bit = 0 ti010 pin input 11: both edges capture operation of cr000 interrupt signal inttm000 signal is not generated even if value is captured. interrupt signal inttm000 signal is generated each time value is captured. set values of es001 and es000 position of edge to be captured 01: rising 00: falling ti000 pin input note 11: both edges capture operation of cr010 interrupt signal inttm010 signal is generated each time value is captured. note the capture operation of cr010 is not affected by the setting of the crc001 bit. caution to capture the count value of the tm00 regi ster to the cr000 register by using the phase reverse to that input to the ti 000 pin, the interrupt request si gnal (inttm000) is not generated after the value has been captured. if the valid edge is de tected on the ti010 pin during this operation, the capture operation is not performed but the inttm 000 signal is generated as an external interrupt signal. to not use th e external interrupt, mask the inttm000 signal. remark crc001: see 6.3 (2) capture/compare control register 00 (crc00) . es101, es100, es001, es000: see 6.3 (4) prescaler mode register 00 (prm00) . chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 121 6.3 registers controlling 16- bit timer/event counter 00 registers used to control 16-bit time r/event counter 00 are shown below. ? 16-bit timer mode control register 00 (tmc00) ? capture/compare contro l register 00 (crc00) ? 16-bit timer output control register 00 (toc00) ? prescaler mode register 00 (prm00) ? port mode register 0 (pm0) ? port register 0 (p0) ? port output mode register 0 (pom0) (1) 16-bit timer mode control register 00 (tmc00) tmc00 is an 8-bit register that sets the 16-bit time r/event counter 00 operation mode, tm00 clear mode, and output timing, and detects an overflow. rewriting tmc00 is prohibited during operation (when tm c003 and tmc002 = other than 00). however, it can be changed when tmc003 and tmc002 are cleared to 00 (s topping operation) and when ovf00 is cleared to 0. tmc00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets tmc00 to 00h. caution 16-bit timer/event counter 00 starts operati on at the moment tmc002 and tmc003 are set to values other than 00 (operation stop mode), respectively. set tmc002 and tmc003 to 00 to stop the operation. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 122 figure 6-5. format of 16-bit timer mode control register 00 (tmc00) address: ffbah after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> tmc00 0 0 0 0 tmc003 tmc002 tmc001 ovf00 tmc003 tmc002 operation enable of 16-bit timer/event counter 00 0 0 disables 16-bit timer/event counter 00 ope ration. stops supplyi ng operating clock. clears 16-bit timer counter 00 (tm00). 0 1 free-running timer mode 1 0 clear & start mode entered by ti000 pin valid edge input note 1 1 clear & start mode entered upon a match between tm00 and cr000 tmc001 condition to reverse timer output (to00) 0 ? match between tm00 and cr000 or match between tm00 and cr010 1 ? match between tm00 and cr000 or match between tm00 and cr010 ? trigger input of ti000 pin valid edge ovf00 tm00 overflow flag clear (0) clears ovf00 to 0 or tmc003 and tmc002 = 00 set (1) overflow occurs. ovf00 is set to 1 when the value of tm00 changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti000 pin valid edge input, and clear & start mode entered upon a match between tm00 and cr000). it can also be set to 1 by writing 1 to ovf00. note the ti000 pin valid edge is set by bits 5 and 4 ( es001, es000) of prescaler mode register 00 (prm00). chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 123 (2) capture/compare control register 00 (crc00) crc00 is the register that controls the operation of cr000 and cr010. changing the value of crc00 is prohibited during oper ation (when tmc003 and tmc002 = other than 00). crc00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears crc00 to 00h. figure 6-6. format of capture/comp are control register 00 (crc00) address: ffbch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc00 0 0 0 0 0 crc002 crc001 crc000 crc002 cr010 operating mode selection 0 operates as compare register 1 operates as capture register crc001 cr000 capture trigger selection 0 captures on valid edge of ti010 pin 1 captures on valid edge of ti000 pin by reverse phase note the valid edge of the ti010 and ti000 pin is set by prm00. if es001 and es000 are set to 11 (both edges) when crc001 is 1, the valid edge of the ti000 pin cannot be detected. crc000 cr000 operating mode selection 0 operates as compare register 1 operates as capture register if tmc003 and tmc002 are set to 11 (clear & start mode entered upon a match between tm00 and cr000), be sure to set crc000 to 0. note when the valid edge is detected from the ti010 pin, the capture opera tion is not performed but the inttm000 signal is generated as an external interrupt signal. caution to ensure that the capture operation is perf ormed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (prm00). chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 124 figure 6-7. example of cr010 capture operat ion (when rising edge is specified) count clock tm00 ti000 rising edge detection cr010 inttm010 n ? 3n ? 2n ? 1 n n + 1 n valid edge (3) 16-bit timer output control register 00 (toc00) toc00 is an 8-bit register t hat controls to00 output. toc00 can be rewritten while only ospt00 is oper ating (when tmc003 and tmc002 = other than 00). rewriting the other bits is prohibited during operation. however, toc004 can be rewritten during timer operation as a means to rewrite cr010 (see 6.5.1 rewriting cr010 during tm00 operation ). toc00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears toc00 to 00h. caution be sure to set toc00 using the following procedure. <1> set toc004 and toc001 to 1. <2> set only toe00 to 1. <3> set either of lvs00 or lvr00 to 1. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 125 figure 6-8. format of 16-bit timer ou tput control register 00 (toc00) address: ffbdh after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc00 0 ospt00 ospe00 toc004 lvs00 lvr00 toc001 toe00 ospt00 one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always ?0? when it is read. do not set this bit to 1 in a mode other than the one- shot pulse output mode. if it is set to 1, tm00 is cleared and started. ospe00 one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti000 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between tm00 and cr000. toc004 to00 output control on match between cr010 and tm00 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm010) is generated even when toc004 = 0. lvs00 lvr00 setting of to00 output status 0 0 no change 0 1 initial value of to00 output is low level (to00 output is cleared to 0). 1 0 initial value of to00 output is high level (to00 output is set to 1). 1 1 setting prohibited ? lvs00 and lvr00 can be used to set the initial value of the to00 output level. if the initial value does not have to be set, leave lvs00 and lvr00 as 00. ? be sure to set lvs00 and lvr00 when toe00 = 1. lvs00, lvr00, and toe00 being simultaneously set to 1 is prohibited. ? lvs00 and lvr00 are trigger bits. by setting these bits to 1, the initial value of the to00 output level can be set. even if these bits are cleared to 0, to00 output is not affected. ? the values of lvs00 and lvr00 are always 0 when they are read. ? for how to set lvs00 and lvr00, see 6.5.2 setting lvs00 and lvr00 . ? the actual to00/ti010/rxd6/p03 pin output is determined depending on pm03 and p03, besides to00 output. toc001 to00 output control on match between cr000 and tm00 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm000) is generated even when toc001 = 0. toe00 to00 output control 0 disables output (to00 output fixed to low level) 1 enables output chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 126 (4) prescaler mode register 00 (prm00) prm00 is the register that se ts the tm00 count clock and ti000 and ti010 pin input valid edges. rewriting prm00 is prohibited during operati on (when tmc003 and tmc002 = other than 00). prm00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears prm00 to 00h. cautions 1. do not apply the following setting when setting the prm001 and prm000 bits to 11 (to specify the valid edge of th e ti000 pin as a count clock). ? clear & start mode entered by the ti000 pin valid edge ? setting the ti000 pin as a capture trigger 2. if the operation of the 16- bit timer/event counter 00 is enable d when the ti000 or ti010 pin is at high level and when the valid edge of the ti000 or ti010 pin is specified to be the rising edge or both edges, th e high level of the ti000 or ti010 pi n is detected as a rising edge. note this when the ti000 or ti010 pin is pulled up. however, the rising edge is not detected when the timer operation has been once stopped and then is enabled again. 3. the valid edge of ti010 and timer output (to 00) cannot be used for the p03 pin at the same time. select either of the functions. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 127 figure 6-9. format of prescaler mode register 00 (prm00) address: ffbbh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm00 es101 es100 es001 es000 0 0 prm001 prm000 es101 es100 ti010 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es001 es000 ti000 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges count clock selection prm001 prm000 f prs = 2 mhz f prs = 4 mhz 0 0 f prs 2 mhz 4 mhz 0 1 f prs /2 2 500 khz 1 mhz 1 0 f prs /2 8 7.81 khz 15.625 khz 1 1 ti000 valid edge note note the external clock from the ti000 pin requires a pulse longer than twice t he cycle of the peripheral hardware clock (f prs ). remark f prs : peripheral hardware clock frequency chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 128 (5) port mode register 0 (pm0) this register sets port 0 input/output in 1-bit units. when using the p03/to00/ti010/rxd6 pin for timer out put, set pm03 and the output latches of p03 to 0. when using the p02/ti000/txd6 and p0 3/to00/ti010/rxd6 pins for timer input, set pm02 and pm03 to 1. at this time, the output latches of p02 and p03 may be 0 or 1. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm0 to ffh. figure 6-10. format of port mode register 0 (pm0) 7 pm07 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 symbol pm0 address: ff20h after reset: ffh r/w pm0n 0 1 p0n pin i/o mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) (6) port output mode resistors (pom0) this register set the output mode of port 0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to 00h. figure 6-11. format of pull-up resistor option register 7 pom07 symbol pom0 6 pom06 5 pom05 4 pom04 3 pom03 2 pom02 1 pom01 0 pom00 address ff38h after reset 00h r/w r/w pom0n p0n pin output mode selection (n = 0 to 7) 0 cmos output 1 n-ch open-drain output (p07:p-ch open-drain output) chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 129 6.4 operation of 16-bit timer/event counter 00 6.4.1 interval timer operation if bits 3 and 2 (tmc003 and tmc002) of the 16-bit timer mode co ntrol register (tmc00) are set to 11 (clear & start mode entered upon a match between tm00 and cr000), the count operation is started in synchronization with the count clock. when the value of tm00 later matches the value of cr000, tm00 is cleared to 0000h and a match interrupt signal (inttm000) is generated. this inttm000 signal ena bles tm00 to operate as an interval timer. remarks 1. for the setting of i/o pins, see 6.3 (5) port mode register 0 (pm0) and (6) port output mode resistors (pom0) . 2. for how to enable the inttm000 interrupt, see chapter 11 interrupt functions . figure 6-12. block diagram of interval timer operation figure 6-13. basic timing exampl e of interval timer operation tm00 register 0000h operable bits (tmc003, tmc002) compare register (cr000) compare match interrupt (inttm000) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) 16-bit counter (tm00) cr000 register operable bits tmc003, tmc002 count clock clear match signal inttm000 signal chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 130 figure 6-14. example of register se ttings for interval timer operation (a) 16-bit timer mode control register 00 (tmc00) 00001100 tmc003 tmc002 tmc001 ovf00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 00000000 crc002 crc001 crc000 cr000 used as compare register (c) 16-bit timer output control register 00 (toc00) 00000 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 000 (d) prescaler mode register 00 (prm00) 00000 3 2 prm001 prm000 es101 es100 es001 es000 selects count clock 0 0/1 0/1 (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) if m is set to cr000, the interval time is as follows. ? interval time = (m + 1) count clock cycle setting cr000 to 0000h is prohibited. (g) 16-bit capture/compare register 010 (cr010) usually, cr010 is not used for the interval timer func tion. however, a compare match interrupt (inttm010) is generated when the set value of cr010 matches the value of tm00. therefore, mask the interrupt request by using the interrupt mask flag (tmmk010). chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 131 figure 6-15. example of software pr ocessing for interval timer function tm00 register 0000h operable bits (tmc003, tmc002) cr000 register inttm000 signal n 11 00 n n n <1> <2> tmc003, tmc002 bits = 11 tmc003, tmc002 bits = 00 register initial setting prm00 register, crc00 register, cr000 register, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. start stop <1> count operation start flow <2> count operation stop flow chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 132 6.4.2 square wave output operation when 16-bit timer/event counter 00 operates as an interval timer (see 6.4.1 ), a square wave can be output from the to00 pin by setting the 16-bit timer output control register 00 (toc00) to 03h. when tmc003 and tmc002 are set to 11 (count clear & start mode entered upon a match between tm00 and cr000), the counting operation is started in synchronizat ion with the count clock. when the value of tm00 later matches the value of cr000, tm00 is cleared to 0000h, an interrupt signal (inttm000) is generated, and to00 output is inverted. this to00 output that is inverted at fixed intervals enables to00 to output a square wave. remarks 1. for the setting of i/o pins, see 6.3 (5) port mode register 0 (pm0) and (6) port output mode resistors (pom0) . 2. for how to enable the inttm000 signal interrupt, see chapter 11 interrupt functions . figure 6-16. block diagram of square wave output operation 16-bit counter (tm00) cr000 register operable bits tmc003, tmc002 count clock clear match signal to00 output inttm000 signal output controller to00 pin figure 6-17. basic timing example of square wave output operation tm00 register 0000h operable bits (tmc003, tmc002) compare register (cr000) to00 output compare match interrupt (inttm000) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 133 figure 6-18. example of register setti ngs for square wave output operation (a) 16-bit timer mode control register 00 (tmc00) 00001100 tmc003 tmc002 tmc001 ovf00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 00000000 crc002 crc001 crc000 cr000 used as compare register (c) 16-bit timer output control register 00 (toc00) 0 0 0 0 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 enables to00 output. inverts to00 output on match between tm00 and cr000. 0/1 1 1 specifies initial value of to00 output f/f (d) prescaler mode register 00 (prm00) 00000 3 2 prm001 prm000 es101 es100 es001 es000 selects count clock 0 0/1 0/1 (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) if m is set to cr000, the interval time is as follows. ? square wave frequency = 1 / [2 (m + 1) count clock cycle] setting cr000 to 0000h is prohibited. (g) 16-bit capture/compare register 010 (cr010) usually, cr010 is not used for the square wave outpu t function. however, a compare match interrupt (inttm010) is generated when the set valu e of cr010 matches the value of tm00. therefore, mask the interrupt request by using the interrupt mask flag (tmmk010). chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 134 figure 6-19. example of software proce ssing for square wave output function tm00 register 0000h operable bits (tmc003, tmc002) cr000 register to00 output inttm000 signal to00 output control bit (toc001, toe00) tmc003, tmc002 bits = 11 tmc003, tmc002 bits = 00 register initial setting prm00 register, crc00 register, toc00 register note , cr000 register, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. start stop <1> count operation start flow <2> count operation stop flow n 11 00 n n n <1> <2> 00 note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 135 6.4.3 external event counter operation when bits 1 and 0 (prm001 and prm000) of the prescaler m ode register 00 (prm00) are set to 11 (for counting up with the valid edge of the ti000 pin) and bits 3 and 2 (tmc003 and tmc002) of 16-bit timer mode control register 00 (tmc00) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between tm00 and cr000 (inttm000) is generated. to input the external event, the ti000 pin is used. th erefore, the timer/event co unter cannot be used as an external event counter in the clear & start mode enter ed by the ti000 pin valid edge input (when tmc003 and tmc002 = 10). the inttm000 signal is generated with the following timing. ? timing of generation of inttm000 signal (second time or later) = number of times of detection of valid edge of external event (set value of cr000 + 1) however, the first match interrupt immediately after the timer/event counter has start ed operating is generated with the following timing. ? timing of generation of inttm000 signal (first time only) = number of times of detection of valid edge of external event input (set value of cr000 + 2) to detect the valid edge, the signal input to t he ti000 pin is sampled during the clock cycle of f prs . the valid edge is not detected until it is detected two times in a row. t herefore, a noise with a short pul se width can be eliminated. remarks 1. for the setting of i/o pins, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm000 signal interrupt, see chapter 11 interrupt functions . figure 6-20. block diagram of ex ternal event counter operation 16-bit counter (tm00) cr000 register operable bits tmc003, tmc002 clear match signal to00 output inttm000 signal f prs edge detection ti000 pin output controller to00 pin chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 136 figure 6-21. example of register settings in external event counter mode (1/2) (a) 16-bit timer mode control register 00 (tmc00) 00001100 tmc003 tmc002 tmc001 ovf00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 00000000 crc002 crc001 crc000 cr000 used as compare register (c) 16-bit timer output control register 00 (toc00) 0 0 0 0/1 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 0/1 0/1 0/1 0: disables to00 output 1: enables to00 output 00: does not invert to00 output on match between tm00 and cr000/cr010. 01: inverts to00 output on match between tm00 and cr000. 10: inverts to00 output on match between tm00 and cr010. 11: inverts to00 output on match between tm00 and cr000/cr010. specifies initial value of to00 output f/f (d) prescaler mode register 00 (prm00) 0 0 0/1 0/1 0 3 2 prm001 prm000 es101 es100 es001 es000 selects count clock (specifies valid edge of ti000). 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 011 (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) if m is set to cr000, the interrupt signal (inttm000) is generated when the num ber of external events reaches (m + 1). setting cr000 to 0000h is prohibited. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 137 figure 6-21. example of register settings in external event counter mode (2/2) (g) 16-bit capture/compare register 010 (cr010) usually, cr010 is not used in the external event counter mode. however, a compare match interrupt (inttm010) is generated when the set valu e of cr010 matches the value of tm00. therefore, mask the interrupt request by using the interrupt mask flag (tmmk010). figure 6-22. example of software proce ssing in external event counter mode tm00 register 0000h operable bits (tmc003, tmc002) 11 00 n n n tmc003, tmc002 bits = 11 tmc003, tmc002 bits = 00 register initial setting prm00 register, crc00 register, toc00 register note , cr000 register, port setting start stop <1> <2> compare match interrupt (inttm000) compare register (cr000) to00 output control bits (toc004, toc001, toe00) to00 output n 00 initial setting of these registers is performed before setting the tmc003 and tmc002 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. <1> count operation start flow <2> count operation stop flow note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 138 6.4.4 operation in clear & start mode entered by ti000 pin valid edge input when bits 3 and 2 (tmc003 and tmc002) of 16-bit timer mode control register 00 (tmc00) are set to 10 (clear & start mode entered by the ti000 pin va lid edge input) and the count clock (set by prm00) is supplied to the timer/event counter, tm00 starts counti ng up. when the valid edge of the ti 000 pin is detected during the counting operation, tm00 is cleared to 0000h a nd starts counting up again. if the valid edge of the ti000 pin is not detected, tm00 overflows and continues counting. the valid edge of the ti000 pin is a c ause to clear tm00. starting the counter is not controlled immediately after the start of the operation. cr000 and cr010 are used as compare registers and capture registers. (a) when cr000 and cr010 are used as compare registers signals inttm000 and inttm010 are generated when the va lue of tm00 matches the value of cr000 and cr010. (b) when cr000 and cr010 are used as capture registers the count value of tm00 is captur ed to cr000 and the inttm000 signal is generated when the valid edge is input to the ti010 pin (or when the phase reverse to that of the valid edge is input to the ti000 pin). when the valid edge is input to t he ti000 pin, the count value of tm00 is captured to cr010 and the inttm010 signal is generated. as soon as the count value has been captured, t he counter is cleared to 0000h. caution do not set the count clo ck as the valid edge of the ti000 pi n (prm001 and prm000 = 11). when prm001 and prm000 = 11, tm00 is cleared. remarks 1. for the setting of the i/o pins, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm000 signal interrupt, see chapter 11 interrupt functions . (1) operation in clear & start mode en tered by ti000 pin valid edge input (cr000: compare register , cr010: compare register) figure 6-23. block diagram of clear & start mode entered by ti000 pin valid edge input (cr000: compare register, cr010: compare register) timer counter (tm00) clear output controller edge detection compare register (cr010) match signal to00 output to00 pin match signal interrupt signal (inttm000) interrupt signal (inttm010) ti000 pin compare register (cr000) operable bits tmc003, tmc002 count clock chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 139 figure 6-24. timing example of clear & star t mode entered by ti000 pin valid edge input (cr000: compare register, cr010: compare register) (a) toc00 = 13h, prm00 = 10h, crc00, = 00h, tmc00 = 08h tm00 register 0000h operable bits (tmc003, tmc002) count clear input (ti000 pin input) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to0 0 output m 10 m nn nn mmm 00 n (b) toc00 = 13h, prm00 = 10h, crc00, = 00h, tmc00 = 0ah tm00 register 0000h operable bits (tmc003, tmc002) count clear input (ti000 pin input) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output m 10 m nn nn mmm 00 n (a) and (b) differ as follows depending on the setting of bi t 1 (tmc001) of 16-bit timer mode control register 01 (tmc00). (a) the to00 output level is inverted wh en tm00 matches a compare register. (b) the to00 output level is inverted when tm00 matches a compare register or when the valid edge of the ti000 pin is detected. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 140 (2) operation in clear & start mode en tered by ti000 pin valid edge input (cr000: compare register , cr010: capture register) figure 6-25. block diagram of clear & start mode entered by ti000 pin valid edge input (cr000: compare register, cr010: capture register) timer counter (tm00) clear output controller edge detector capture register (cr010) capture signal to00 pin match signal to00 output interrupt signal (inttm000) interrupt signal (inttm010) ti000 pin compare register (cr000) operable bits tmc003, tmc002 count clock figure 6-26. timing example of clear & star t mode entered by ti000 pin valid edge input (cr000: compare register, cr010: capture register) (1/2) (a) toc00 = 13h, prm00 = 10h, crc00 = 04h, tmc00 = 08h, cr000 = 0001h tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) compare register (cr000) compare match interrupt (inttm000) capture register (cr010) capture interrupt (inttm010) to00 output 0001h 10 q p n m s 00 0000h m n s p q this is an application example where the to00 output level is inverted w hen the count value has been captured & cleared. the count value is captured to cr010 and tm00 is cleared (to 0000h) when the valid edge of the ti000 pin is detected. when the count value of tm00 is 0001h, a compare match interr upt signal (inttm000) is generated, and the to00 output level is inverted. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 141 figure 6-26. timing example of clear & star t mode entered by ti000 pin valid edge input (cr000: compare register, cr010: capture register) (2/2) (b) toc00 = 13h, prm00 = 10h, crc00 = 04h, tmc00 = 0ah, cr000 = 0003h tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) compare register (cr000) compare match interrupt (inttm000) capture register (cr010) capture interrupt (inttm010) to00 output 0003h 0003h 10 q p n m s 00 0000h m 4444 ns pq this is an application exampl e where the width set to cr0 00 (4 clocks in this example) is to be output from the to00 pin when the count value has been captured & cleared. the count value is captured to cr010, a capture interr upt signal (inttm010) is gener ated, tm00 is cleared (to 0000h), and the to00 output level is inverted when the valid edge of the ti000 pin is detected. when the count value of tm00 is 0003h (four clocks have been counted), a compare match interrupt signal (inttm000) is generated and the to00 outpu t level is inverted. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 142 (3) operation in clear & start mode en tered by ti000 pin valid edge input (cr000: capture register , cr010: compare register) figure 6-27. block diagram of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: compare register) timer counter (tm00) clear output controller edge detection capture register (cr000) capture signal to00 pin match signal to00 output interrupt signal (inttm010) interrupt signal (inttm000) ti000 pin compare register (cr010) operable bits tmc003, tmc002 count clock chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 143 figure 6-28. timing example of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: compare register) (1/2) (a) toc00 = 13h, prm00 = 10h, crc00 = 03h, tmc00 = 08h, cr010 = 0001h tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) capture register (cr000) capture interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output 10 p n m s 00 l 0001h 0000h mns p this is an application example where the to00 output le vel is to be inverted when the count value has been captured & cleared. tm00 is cleared at the rising edge det ection of the ti000 pin and it is captured to cr000 at the falling edge detection of the ti000 pin. when bit 1 (crc001) of capture/compare control register 00 (crc00) is set to 1, the count value of tm00 is captured to cr000 in the phase reverse to that of the signa l input to the ti000 pin, but the capture interrupt signal (inttm000) is not generated. however, the inttm000 sig nal is generated when the valid edge of the ti010 pin is detected. mask the inttm000 signal when it is not used. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 144 figure 6-28. timing example of clear & star t mode entered by ti000 pin valid edge input (cr000: capture register, cr010: compare register) (2/2) (b) toc00 = 13h, prm00 = 10h, crc00 = 03h, tmc00 = 0ah, cr010 = 0003h tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) capture register (cr000) capture interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output 0003h 0003h 10 p n m s 00 4444 l 0000h m n s p this is an application exampl e where the width set to cr0 10 (4 clocks in this example) is to be output from the to00 pin when the count value has been captured & cleared. tm00 is cleared (to 0000h) at the rising edge detection of the ti000 pin and captur ed to cr000 at the falling edge detection of the ti000 pin. t he to00 output level is inverted when tm00 is cleared (to 0000h) because the rising edge of the ti000 pin has been detected or when t he value of tm00 matches that of a compare register (cr010). when bit 1 (crc001) of capture/compare control register 00 (crc00) is 1, the count value of tm00 is captured to cr000 in the phase reverse to that of the input si gnal of the ti000 pin, but th e capture interrupt signal (inttm000) is not generated. however, the inttm000 inte rrupt is generated when t he valid edge of the ti010 pin is detected. mask the inttm000 signal when it is not used. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 145 (4) operation in clear & start mode en tered by ti000 pin valid edge input (cr000: capture register , cr010: capture register) figure 6-29. block diagram of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: capture register) timer counter (tm00) clear to00 output output controller capture register (cr000) capture signal capture signal to00 pin note interrupt signal (inttm010) interrupt signal (inttm000) capture register (cr010) operable bits tmc003, tmc002 count clock edge detection ti000 pin edge detection ti010 pin note selector note the timer output (to00) cannot be used when det ecting the valid edge of the ti010 pin is used. figure 6-30. timing example of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: capture register) (1/3) (a) toc00 = 13h, prm00 = 30h, crc00 = 05h, tmc00 = 0ah tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) capture register (cr000) capture interrupt (inttm000) capture register (cr010) capture interrupt (inttm010) to00 output 10 r s t o l m n p q 00 l 0000h 0000h lm nopqrst this is an application example where the count value is captured to cr010, tm00 is cleared, and to00 output is inverted when the rising or falli ng edge of the ti000 pin is detected. when the edge of the ti010 pin is det ected, an interrupt signal (inttm000) is generated. mask the inttm000 signal when it is not used. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 146 figure 6-30. timing example of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: capture register) (2/3) (b) toc00 = 13h, prm00 = c0h, crc00 = 05h, tmc00 = 0ah tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti010 pin input) capture register (cr000) capture interrupt (inttm000) capture & count clear input (ti000) capture register (cr010) capture interrupt (inttm010) 10 r s t o l m n p q 00 ffffh l l 0000h 0000h lmn o pq r s t this is a timing example where an edge is not input to the ti000 pin, in an applicatio n where the count value is captured to cr000 when the rising or fa lling edge of the ti010 pin is detected. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 147 figure 6-30. timing example of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: capture register) (3/3) (c) toc00 = 13h, prm00 = 00h, crc00 = 07h, tmc00 = 0ah tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) capture register (cr000) capture register (cr010) capture interrupt (inttm010) capture input (ti010) capture interrupt (inttm000) 0000h 10 p o m q r t s w n l 00 l l ln r pt 0000h moq sw this is an application example where the pulse width of the signal input to the ti000 pin is measured. by setting crc00, the count value can be captured to cr000 in the phase reverse to the falling edge of the ti000 pin (i.e., rising edge) and to cr010 at the falling edge of the ti000 pin. the high- and low-level widths of the input pulse can be calculated by the following expressions. ? high-level width = [cr010 value] ? [cr000 value] [count clock cycle] ? low-level width = [cr000 value] [count clock cycle] if the reverse phase of the ti000 pin is selected as a tri gger to capture the count value to cr000, the inttm000 signal is not generated. read the values of cr000 an d cr010 to measure the pulse width immediately after the inttm010 signal is generated. however, if the valid edge specified by bits 6 and 5 (e s101 and es100) of prescaler mode register 00 (prm00) is input to the ti010 pin, the count value is not captured but the inttm00 0 signal is generated. to measure the pulse width of the ti000 pin, mask the inttm000 signal when it is not used. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 148 figure 6-31. example of register settings in clear & st art mode entered by ti000 pin valid edge input (1/2) (a) 16-bit timer mode control register 00 (tmc00) 0000100/10 tmc003 tmc002 tmc001 ovf00 clears and starts at valid edge input of ti000 pin. 0: inverts to00 output on match between tm00 and cr000/cr010. 1: inverts to00 output on match between tm00 and cr000/cr010 and valid edge of ti000 pin. (b) capture/compare cont rol register 00 (crc00) 000000/10/10/1 crc002 crc001 crc000 0: cr000 used as compare register 1: cr000 used as capture register 0: cr010 used as compare register 1: cr010 used as capture register 0: ti010 pin is used as capture trigger of cr000. 1: reverse phase of ti000 pin is used as capture trigger of cr000. (c) 16-bit timer output control register 00 (toc00) 0 0 0 0/1 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 0: disables to00 output note 1: enables to00 output 00: does not invert to00 output on match between tm00 and cr000/cr010. 01: inverts to00 output on match between tm00 and cr000. 10: inverts to00 output on match between tm00 and cr010. 11: inverts to00 output on match between tm00 and cr000/cr010. specifies initial value of to00 output f/f 0/1 0/1 0/1 note the timer output (to00) cannot be used when det ecting the valid edge of the ti010 pin is used. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 149 figure 6-31. example of register settings in clear & st art mode entered by ti000 pin valid edge input (2/2) (d) prescaler mode register 00 (prm00) 0/1 0/1 0/1 0/1 0 3 2 prm001 prm000 es101 es100 es001 es000 count clock selection (setting ti000 valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc001 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) when this register is used as a compare register an d when its value matches the count value of tm00, an interrupt signal (inttm000) is generated. the count value of tm00 is not cleared. to use this register as a capture regist er, select either the ti000 or ti010 pin note input as a capture trigger. when the valid edge of the capture tr igger is detected, the count va lue of tm00 is stored in cr000. note the timer output (to00) cannot be used when detection of the vali d edge of the ti010 pin is used. (g) 16-bit capture/compare register 010 (cr010) when this register is used as a compare register an d when its value matches the count value of tm00, an interrupt signal (inttm010) is generated. the count value of tm00 is not cleared. when this register is used as a capt ure register, the ti000 pi n input is used as a capture trigger. when the valid edge of the capture trigger is detected, the count value of tm00 is stored in cr010. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 150 figure 6-32. example of software processing in clear & start mode entered by ti000 pin valid edge input tm00 register 0000h operable bits (tmc003, tmc002) count clear input (ti000 pin input) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output m 10 m n n n n mmm 00 <1> <2> <2> <2> <3> <2> 00 n tmc003, tmc002 bits = 10 edge input to ti000 pin register initial setting prm00 register, crc00 register, toc0 0 register note , cr000, cr010 registers, tmc00.tmc001 bit, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits to 10. starts count operation when the valid edge is input to the ti000 pin, the value of the tm00 register is cleared. start <1> count operation start flow <2> tm00 register clear & start flow tmc003, tmc002 bits = 00 the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. stop <3> count operation stop flow note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 151 6.4.5 free-running timer operation when bits 3 and 2 (tmc003 and tmc002) of 16-bit timer mode control register 00 (t mc00) are set to 01 (free- running timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock. when it has counted up to ffffh, the over flow flag (ovf00) is set to 1 at t he next clock, and tm00 is cleared (to 0000h) and continues counting. clear ovf00 to 0 by executing the clr instruction via software. the following three types of free-runn ing timer operations are available. ? both cr000 and cr010 are used as compare registers. ? one of cr000 or cr010 is used as a compare regi ster and the other is us ed as a capture register. ? both cr000 and cr010 are used as capture registers. remarks 1. for the setting of the i/o pins, see 6.3 (5) port mode register 0 (pm0) and (6) port output mode resistors (pom0) . 2. for how to enable the inttm000 signal interrupt, see chapter 11 interrupt functions . (1) free-running timer mode operation (cr000: compare register , cr010: compare register) figure 6-33. block diagram of free-running timer mode (cr000: compare register, cr010: compare register) timer counter (tm00) output controller compare register (cr010) match signal to00 pin match signal to00 output interrupt signal (inttm000) interrupt signal (inttm010) compare register (cr000) operable bits tmc003, tmc002 count clock chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 152 figure 6-34. timing example of free-running timer mode (cr000: compare register, cr010: compare register) ? toc00 = 13h, prm00 = 00h, crc00 = 00h, tmc00 = 04h ffffh tm00 register 0000h operable bits (tmc003, tmc002) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output ovf00 bit 01 m n m n m n m n 00 00 n 0 write clear 0 write clear 0 write clear 0 write clear m this is an application example where two compare registers are used in the free-running timer mode. the to00 output level is inverted each time the count valu e of tm00 matches the set value of cr000 or cr010. when the count value matches the register val ue, the inttm000 or inttm010 signal is generated. (2) free-running timer mode operation (cr000: compare register , cr010: capture register) figure 6-35. block diagram of free-running timer mode (cr000: compare register, cr010: capture register) timer counter (tm00) output controller edge detection capture register (cr010) capture signal to00 pin match signal to00 output interrupt signal (inttm000) interrupt signal (inttm010) ti000 pin compare register (cr000) operable bits tmc003, tmc002 count clock chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 153 figure 6-36. timing example of free-running timer mode (cr000: compare register, cr010: capture register) ? toc00 = 13h, prm00 = 10h, crc00 = 04h, tmc00 = 04h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti000) compare register (cr000) compare match interrupt (inttm000) capture register (cr010) capture interrupt (inttm010) to00 output overflow flag (ovf00) 0 write clear 0 write clear 0 write clear 0 write clear 01 m n s p q 00 0000h 0000h mn s p q this is an application example where a compare register an d a capture register are used at the same time in the free-running timer mode. in this example, the inttm000 signal is generated an d the to00 output level is inverted each time the count value of tm00 matches the set value of cr000 (compar e register). in addition, the inttm010 signal is generated and the count value of tm00 is captured to cr010 each time the valid edge of the ti000 pin is detected. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 154 (3) free-running timer mode operation (cr000: capture register , cr010: capture register) figure 6-37. block diagram of free-running timer mode (cr000: capture register, cr010: capture register) timer counter (tm00) capture register (cr000) capture signal capture signal interrupt signal (inttm010) interrupt signal (inttm000) capture register (cr010) operable bits tmc003, tmc002 count clock edge detection ti000 pin edge detection ti010 pin selector remark if both cr000 and cr010 are used as capture regist ers in the free-running timer mode, the to00 output level is not inverted. however, it can be inverted each time the valid e dge of the ti000 pin is detec ted if bit 1 (tmc001) of 16-bit timer mode control register 00 (tmc00) is set to 1. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 155 figure 6-38. timing example of free-running timer mode (cr000: capture register, cr010: capture register) (1/2) (a) toc00 = 13h, prm00 = 50h, crc00 = 05h, tmc00 = 04h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti000) capture register (cr010) capture interrupt (inttm010) capture trigger input (ti010) capture register (cr000) capture interrupt (inttm000) overflow flag (ovf00) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h abc d e 0000h mn s p q this is an application example where the count values that have been captured at the valid edges of separate capture trigger signals are stor ed in separate capture registers in the free-running timer mode. the count value is captured to cr010 when the valid edge of the ti000 pi n input is detected and to cr000 when the valid edge of the ti010 pin input is detected. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 156 figure 6-38. timing example of free-running timer mode (cr000: capture register, cr010: capture register) (2/2) (b) toc00 = 13h, prm00 = c0h, crc00 = 05h, tmc00 = 04h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti010) capture register (cr000) capture interrupt (inttm000) capture trigger input (ti000) capture register (cr010) capture interrupt (inttm010) 01 l m p s n o r q t 00 0000h 0000h lmn o pq r s t l l this is an application example wh ere both the edges of the ti010 pin ar e detected and the count value is captured to cr000 in the free-running timer mode. when both cr000 and cr010 are used as capture register s and when the valid edge of only the ti010 pin is to be detected, the count value cannot be captured to cr010. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 157 figure 6-39. example of register setti ngs in free-running timer mode (1/2) (a) 16-bit timer mode control register 00 (tmc00) 0000010/10 tmc003 tmc002 tmc001 ovf00 free-running timer mode 0: inverts to00 output on match between tm00 and cr000/cr010. 1: inverts to00 output on match between tm00 and cr000/cr010 and valid edge of ti000 pin. (b) capture/compare cont rol register 00 (crc00) 000000/10/10/1 crc002 crc001 crc000 0: cr000 used as compare register 1: cr000 used as capture register 0: cr010 used as compare register 1: cr010 used as capture register 0: ti010 pin is used as capture trigger of cr000. 1: reverse phase of ti000 pin is used as capture trigger of cr000. (c) 16-bit timer output control register 00 (toc00) 0 0 0 0/1 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 0: disables to00 output 1: enables to00 output 00: does not invert to00 output on match between tm00 and cr000/cr010. 01: inverts to00 output on match between tm00 and cr000. 10: inverts to00 output on match between tm00 and cr010. 11: inverts to00 output on match between tm00 and cr000/cr010. specifies initial value of to00 output f/f 0/1 0/1 0/1 chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 158 figure 6-39. example of register setti ngs in free-running timer mode (2/2) (d) prescaler mode register 00 (prm00) 0/1 0/1 0/1 0/1 0 3 2 prm001 prm000 es101 es100 es001 es000 count clock selection (setting ti000 valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc001 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) when this register is used as a compare register an d when its value matches the count value of tm00, an interrupt signal (inttm000) is generated. the count value of tm00 is not cleared. to use this register as a capture register, select ei ther the ti000 or ti010 pin in put as a capture trigger. when the valid edge of the capture tr igger is detected, the count va lue of tm00 is stored in cr000. (g) 16-bit capture/compare register 010 (cr010) when this register is used as a compare register an d when its value matches the count value of tm00, an interrupt signal (inttm010) is generated. the count value of tm00 is not cleared. when this register is used as a capt ure register, the ti000 pi n input is used as a capture trigger. when the valid edge of the capture trigger is detected, the count value of tm00 is stored in cr010. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 159 figure 6-40. example of software pr ocessing in free-running timer mode ffffh tm00 register 0000h operable bits (tmc003, tmc002) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) timer output control bits (toe0, toc004, toc001) to00 output m 01 n n n n m m m 00 <1> <2> 00 n tmc003, tmc002 bits = 0, 1 register initial setting prm00 register, crc00 register, toc00 register note , cr000/cr010 register, tmc00.tmc001 bit, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits to 01. starts count operation start <1> count operation start flow tmc003, tmc002 bits = 0, 0 the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. stop <2> count operation stop flow note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 160 6.4.6 ppg output operation a square wave having a pulse width set in advance by cr010 is output from the to00 pin as a ppg (programmable pulse generator) signal during a cycle set by cr000 when bits 3 and 2 (tmc003 and tmc002) of 16- bit timer mode control register 00 (tmc00) are set to 11 (clear & start upon a match between tm00 and cr000). the pulse cycle and duty factor of the pulse generated as the ppg output are as follows. ? pulse cycle = (set value of cr000 + 1) count clock cycle ? duty = (set value of cr010 + 1) / (set value of cr000 + 1) caution to change the duty factor (value of cr010) during operation, see 6.5. 1 rewriting cr010 during tm00 operation. remarks 1. for the setting of i/o pins, see 6.3 (5) port mode register 0 (pm0) and (6) port output mode resistors (pom0) . 2. for how to enable the inttm000 signal interrupt, see chapter 11 interrupt functions . figure 6-41. block diagram of ppg output operation timer counter (tm00) clear output controller compare register (cr010) match signal to00 pin match signal to00 output interrupt signal (inttm000) interrupt signal (inttm010) compare register (cr000) operable bits tmc003, tmc002 count clock chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 161 figure 6-42. example of register settings for ppg output operation (a) 16-bit timer mode control register 00 (tmc00) 00001100 tmc003 tmc002 tmc001 ovf00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 00000000 crc002 crc001 crc000 cr000 used as compare register cr010 used as compare register (c) 16-bit timer output control register 00 (toc00) 0 0 0 1 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 enables to00 output 11: inverts to00 output on match between tm00 and cr000/cr010. 00: disables one-shot pulse output specifies initial value of to00 output f/f 0/1 1 1 (d) prescaler mode register 00 (prm00) 00000 3 2 prm001 prm000 es101 es100 es001 es000 selects count clock 0 0/1 0/1 (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) an interrupt signal (inttm000) is generated when the value of this register matches the count value of tm00. the count value of tm00 is not cleared. (g) 16-bit capture/compare register 010 (cr010) an interrupt signal (inttm010) is generated when the value of this register matches the count value of tm00. the count value of tm00 is not cleared. caution set values to cr000 and cr010 such that the condition 0000h cr010 < cr000 ffffh is satisfied. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 162 figure 6-43. example of software pr ocessing for ppg output operation tm00 register 0000h operable bits (tmc003, tmc002) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) timer output control bits (toe00, toc004, toc001) to00 output m 11 m m m n n n 00 <1> n + 1 <2> 00 n tmc003, tmc002 bits = 11 register initial setting prm00 register, crc00 register, toc00 register note , cr000, cr010 registers, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits. starts count operation start <1> count operation start flow tmc003, tmc002 bits = 00 the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. stop <2> count operation stop flow n + 1 n + 1 m + 1 m + 1 m + 1 note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . remark ppg pulse cycle = (m + 1) count clock cycle ppg duty = (n + 1) / (m + 1) chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 163 6.4.7 one-shot pulse output operation a one-shot pulse can be output by setting bits 3 and 2 (tmc003 and tmc002) of the 16-bit timer mode control register 00 (tmc00) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the ti000 pin valid edge) and setting bit 5 (ospe00) of 16-bit timer ou tput control register 00 (toc00) to 1. when bit 6 (ospt00) of toc00 is set to 1 or when the valid edge is input to the ti000 pin during timer operation, clearing & starting of tm00 is triggered, and a pulse of the difference between the values of cr000 and cr010 is output only once from the to00 pin. cautions 1. do not input the trigger again (setting ospt00 to 1 or detecting the valid edge of the ti000 pin) while the one-shot pulse is output. to out put the one-shot pulse again, generate the trigger after the current one-s hot pulse output has completed. 2. to use only the setting of ospt00 to 1 as the trigger of one-shot pulse output, do not change the level of the ti000 pin or it s alternate function port pin. otherwise, the pulse will be unexpectedly output. remarks 1. for the setting of the i/o pins, see 6.3 (5) port mode register 0 (pm0) and (6) port output mode resistors (pom0) . 2. for how to enable the inttm000 signal interrupt, see chapter 11 interrupt functions . figure 6-44. block diagram of on e-shot pulse output operation timer counter (tm00) output controller compare register (cr010) match signal to00 pin match signal to00 output interrupt signal (inttm000) interrupt signal (inttm010) compare register (cr000) operable bits tmc003, tmc002 count clock ti000 edge detection ospt00 bit ospe00 bit clear chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 164 figure 6-45. example of register settings for one-shot pulse output operation (1/2) (a) 16-bit timer mode control register 00 (tmc00) 00000/10/100 tmc003 tmc002 tmc001 ovf00 01: free running timer mode 10: clear and start mode by valid edge of ti000 pin. (b) capture/compare cont rol register 00 (crc00) 00000000 crc002 crc001 crc000 cr000 used as compare register cr010 used as compare register (c) 16-bit timer output control register 00 (toc00) 0 0/1 1 1 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 enables to00 output inverts to00 output on match between tm00 and cr000/cr010. specifies initial value of to00 output enables one-shot pulse output software trigger is generated by writing 1 to this bit (operation is not affected even if 0 is written to it). 0/1 1 1 (d) prescaler mode register 00 (prm00) 00000 3 2 prm001 prm000 es101 es100 es001 es000 selects count clock 0 0/1 0/1 chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 165 figure 6-45. example of register settings for one-shot pulse output operation (2/2) (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) this register is used as a compar e register when a one-shot pulse is output. when the value of tm00 matches that of cr000, an interrupt signal (inttm000) is generated and the to00 output level is inverted. (g) 16-bit capture/compare register 010 (cr010) this register is used as a compar e register when a one-shot pulse is output. when the value of tm00 matches that of cr010, an interrupt signal (inttm010) is generated and the to00 output level is inverted. caution do not set the same value to cr000 and cr010. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 166 figure 6-46. example of software processing for one-shot pulse output operation (1/2) ffffh tm00 register 0000h operable bits (tmc003, tmc002) one-shot pulse enable bit (ospe0) one-shot pulse trigger bit (ospt0) one-shot pulse trigger input (ti000 pin) overflow plug (ovf00) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output to00 output control bits (toe00, toc004, toc001) n m n ? m n ? m 01 or 10 00 00 n n n m m m m + 1 m + 1 <1> <2> <2> <3> to00 output level is not inverted because no one- shot trigger is input. ? time from when the one-shot pulse trigger is input until the one-shot pulse is output = (m + 1) count clock cycle ? one-shot pulse output active level width = (n ? m) count clock cycle chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 167 figure 6-46. example of software processing for one-shot pulse output operation (2/2) tmc003, tmc002 bits = 01 or 10 register initial setting prm00 register, crc00 register, toc00 register note , cr000, cr010 registers, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits. starts count operation start <1> count operation start flow <2> one-shot trigger input flow tmc003, tmc002 bits = 00 the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. stop <3> count operation stop flow toc00.ospt00 bit = 1 or edge input to ti000 pin write the same value to the bits other than the ostp00 bit. note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 168 6.4.8 pulse width measurement operation tm00 can be used to measure the pulse width of the signal input to the ti000 and ti010 pins. measurement can be accomplished by operating the 16-bit ti mer/event counter 00 in the free-running timer mode or by restarting the timer in synchronizati on with the signal input to the ti000 pin. when an interrupt is generated, read the value of the valid capture register and measure the pulse width. check bit 0 (ovf00) of 16-bit timer mode control register 00 (tmc 00). if it is set (to 1), clear it to 0 by software. figure 6-47. block di agram of pulse width measureme nt (free-running timer mode) timer counter (tm00) capture register (cr000) capture signal capture signal interrupt signal (inttm010) interrupt signal (inttm000) capture register (cr010) operable bits tmc003, tmc002 count clock edge detection ti000 pin edge detection ti010 pin selector figure 6-48. block diagram of pulse width measurement (clear & start mode entered by ti000 pin valid edge input) timer counter (tm00) capture register (cr000) capture signal capture signal interrupt signal (inttm010) interrupt signal (inttm000) capture register (cr010) operable bits tmc003, tmc002 count clock edge detection ti000 pin edge detection ti010 pin clear selector chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 169 a pulse width can be measured in the following three ways. ? measuring the pulse width by using two input signals of the ti000 and ti010 pins (free-running timer mode) ? measuring the pulse width by using one input signal of the ti000 pin (free-running timer mode) ? measuring the pulse width by using one input signal of the ti000 pin (clear & start mode entered by the ti000 pin valid edge input) remarks 1. for the setting of the i/o pins, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm000 signal interrupt, see chapter 11 interrupt functions . (1) measuring the pulse width by using two input si gnals of the ti000 and ti010 pins (free-running timer mode) set the free-running timer mode (tmc003 and tmc002 = 01). when the valid edge of t he ti000 pin is detected, the count value of tm00 is captured to cr010. when the valid edge of the ti 010 pin is detected, the count value of tm00 is captured to cr000. specify detecti on of both the edges of the ti000 and ti010 pins. by this measurement method, the prev ious count value is subt racted from the count valu e captured by the edge of each input signal. therefore, sa ve the previously captured value to a separate register in advance. if an overflow occurs, the value becomes negative if the pr eviously captured value is si mply subtracted from the current captured value and, t herefore, a borrow occurs (bit 0 (cy) of the program status word (psw) is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addition, clear bit 0 (ovf00) of 16-bit timer mode control register 00 (tmc00) to 0. figure 6-49. timing example of pulse width measurement (1) ? tmc00 = 04h, prm00 = f0h, crc00 = 05h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti000) capture register (cr010) capture interrupt (inttm010) capture trigger input (ti010) capture register (cr000) capture interrupt (inttm000) overflow flag (ovf00) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h abc d e 0000h mn s p q chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 170 (2) measuring the pulse width by using one input signal of the ti000 pin (free-running mode) set the free-running timer mode (tmc003 and tmc002 = 01). the count value of tm00 is captured to cr000 in the phase reverse to the valid edge detec ted on the ti000 pin. when the valid edge of the ti000 pin is detected, the count value of tm00 is captured to cr010. by this measurement method, values are stored in se parate capture registers when a width from one edge to another is measured. theref ore, the capture values do not have to be saved. by subtracting the value of one capture register from that of a nother, a high-level width, low-level width, and cycle are calculated. if an overflow occurs, the value becomes negative if one c aptured value is simply subtracted from another and, therefore, a borrow occurs (bit 0 (cy) of the program status word (psw) is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addi tion, clear bit 0 (ovf00) of 16-bit timer mode control register 00 (tmc00) to 0. figure 6-50. timing example of pulse width measurement (2) ? tmc00 = 04h, prm00 = 10h, crc00 = 07h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti000) capture register (cr000) capture register (cr010) capture interrupt (inttm010) overflow flag (ovf00) capture trigger input (ti010) capture interrupt (inttm000) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h l l abc d e 0000h mn s p q chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 171 (3) measuring the pulse width by using one input signal of the ti000 pin (clear & start mode entered by the ti000 pin valid edge input) set the clear & start mode entered by the ti000 pin valid edge (tmc003 and tmc002 = 10). the count value of tm00 is captured to cr000 in the phase reverse to the valid edge of the ti000 pin, and the count value of tm00 is captured to cr010 and tm00 is cleared (0000h) when t he valid edge of the ti000 pin is detected. therefore, a cycle is stored in cr010 if tm00 does not overflow. if an overflow occurs, take the value that results from adding 10000h to the value stored in cr010 as a cycle. clear bit 0 (ovf00) of 16-bit timer mode control register 00 (tmc00) to 0. figure 6-51. timing example of pulse width measurement (3) ? tmc00 = 08h, prm00 = 10h, crc00 = 07h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000) capture register (cr000) capture register (cr010) capture interrupt (inttm010) overflow flag (ovf00) capture trigger input (ti010) capture interrupt (inttm000) 10 <1> <2> <3> <3> <3> <3> <2> <2> <2> <1> <1> <1> m a b cd n s p q 00 00 0 write clear 0000h l l abc d 0000h mn s p q <1> pulse cycle = (10000h number of times ovf00 bit is set to 1 + captured value of cr010) count clock cycle <2> high-level pulse width = (10000h number of times ovf00 bit is set to 1 + captured value of cr000) count clock cycle <3> low-level pulse width = (pulse cycle ? high-level pulse width) chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 172 figure 6-52. example of register setti ngs for pulse width measurement (1/2) (a) 16-bit timer mode control register 00 (tmc00) 00000/10/100 tmc003 tmc002 tmc001 ovf00 01: free running timer mode 10: clear and start mode entered by valid edge of ti000 pin. (b) capture/compare cont rol register 00 (crc00) 0000010/11 crc002 crc001 crc000 1: cr000 used as capture register 1: cr010 used as capture register 0: ti010 pin is used as capture trigger of cr000. 1: reverse phase of ti000 pin is used as capture trigger of cr000. (c) 16-bit timer output control register 00 (toc00) 00000 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 000 (d) prescaler mode register 00 (prm00) 0/1 0/1 0/1 0/1 0 3 2 prm001 prm000 es101 es100 es001 es000 selects count clock (setting valid edge of ti000 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting when crc001 = 1 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 173 figure 6-52. example of register setti ngs for pulse width measurement (2/2) (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) this register is used as a capture register. either th e ti000 or ti010 pin is selected as a capture trigger. when a specified edge of t he capture trigger is detec ted, the count value of tm00 is stored in cr000. (g) 16-bit capture/compare register 010 (cr010) this register is used as a capture register. the signal input to the ti 000 pin is used as a capture trigger. when the capture trigger is detected, the count value of tm00 is stored in cr010. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 174 figure 6-53. example of software proce ssing for pulse width measurement (1/2) (a) example of free-running timer mode ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti000) capture register (cr010) capture interrupt (inttm010) capture trigger input (ti010) capture register (cr000) capture interrupt (inttm000) 01 d 00 d 00 d 01 d 01 d 02 d 02 d 03 d 03 d 04 d 04 d 10 d 10 d 11 d 11 d 12 d 12 d 13 d 13 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <2> <3> (b) example of clear & start mode entered by ti000 pin valid edge ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000) capture register (cr000) capture interrupt (inttm000) capture register (cr010) capture interrupt (inttm010) 10 d 0 l d 0 d 1 d 1 d 2 d 2 d 3 d 3 d 4 d 4 d 5 d 5 d 6 d 6 d 7 d 7 d 8 d 8 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <3> <2> chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 175 figure 6-53. example of software proce ssing for pulse width measurement (2/2) <2> capture trigger input flow edge detection of ti000, ti010 pins calculated pulse width from capture value stores count value to cr000, cr010 registers generates capture interrupt note tmc003, tmc002 bits = 01 or 10 register initial setting prm00 register, crc00 register, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits. starts count operation start <1> count operation start flow tmc003, tmc002 bits = 00 the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. stop <3> count operation stop flow note the capture interrupt signal (in ttm000) is not generated when the reve rse-phase edge of the ti000 pin input is selected to the valid edge of cr000. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 176 6.5 special use of tm00 6.5.1 rewriting cr010 during tm00 operation in principle, rewriting cr000 and cr010 of the pd179f11x, 179f12x microcontrolle rs when they are used as compare registers is prohibited while tm00 is operating (tmc003 and tmc002 = other than 00). however, the value of cr010 can be changed, even while tm00 is operating, using the following procedure if cr010 is used for ppg output and the duty factor is change d. (when changing the value of cr010 to a smaller value than the current one, rewrite it immediately after its value matches the va lue of tm00. when changing the value of cr010 to a larger value than the current one, rewrite it i mmediately after the values of cr000 and tm00 match. if the value of cr010 is rewritten immediately before a ma tch between cr010 and tm00, or between cr000 and tm00, an unexpected operation may be performed.). procedure for changing value of cr010 <1> disable interrupt inttm010 (tmmk010 = 1). <2> disable reversal of the timer output when th e value of tm00 matches that of cr010 (toc004 = 0). <3> change the value of cr010. <4> wait for one cycle of the count clock of tm00. <5> enable reversal of the timer output when the value of tm00 matches that of cr010 (toc004 = 1). <6> clear the interrupt flag of inttm010 (tmif010 = 0) to 0. <7> enable interrupt inttm010 (tmmk010 = 0). remark for tmif010 and tmmk010, see chapter 11 interrupt functions . 6.5.2 setting lvs00 and lvr00 (1) usage of lvs00 and lvr00 lvs00 and lvr00 are used to set the default value of to 00 output and to invert the timer output without enabling the timer operation (tmc003 and tmc002 = 00). clear lvs 00 and lvr00 to 00 (default value: low-level output) when software control is unnecessary. lvs00 lvr00 timer output status 0 0 not changed (low-level output) 0 1 cleared (low-level output) 1 0 set (high-level output) 1 1 setting prohibited chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 177 (2) setting lvs00 and lvr00 set lvs00 and lvr00 using the following procedure. figure 6-54. example of flow for setting lvs00 and lvr00 bits setting toc00.ospe00, toc004, toc001 bits setting toc00.toe00 bit setting toc00.lvs00, lvr00 bits setting tmc00.tmc003, tmc002 bits <3> enabling timer operation <2> setting of timer output f/f <1> setting of timer output operation caution be sure to set lvs00 and lvr00 follo wing steps <1>, <2>, and <3> above. step <2> can be performed after <1> and before <3>. figure 6-55. timing example of lvr00 and lvs00 toc00.lvs00 bit toc00.lvr00 bit operable bits (tmc003, tmc002) to00 output inttm000 signal <1> 00 <2> <1> <3> <4> <4> <4> 01, 10, or 11 <1> to00 output goes high when lvs00 and lvr00 = 10. <2> to00 output goes low when lvs00 and lvr00 = 01 (the pin output remains unchanged from the high level even if lvs00 and lvr00 are cleared to 00). <3> the timer starts operating when tmc003 and tmc002 are set to 01, 10, or 11. because lvs00 and lvr00 were set to 10 before the operat ion was started, to00 out put starts from the high level. after the timer starts operating, setting lvs00 and lvr00 is prohibited until tmc003 and tmc002 = 00 (disabling the timer operation). <4> the to00 output level is inverted each time an interrupt signal (inttm000) is generated. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 178 6.6 cautions for 16-bit timer/event counter 00 (1) restrictions for each channel of 16-bit timer/event counter 00 table 6-3 shows the restrictions for each channel. table 6-3. restrictions for each ch annel of 16-bit timer/event counter 00 operation restriction as interval timer as square wave output as external event counter ? as clear & start mode entered by ti000 pin valid edge input using timer output (to00) is prohibited when det ection of the valid edge of the ti010 pin is used. (toc00 = 00h) as free-running timer ? as ppg output 0000h cr010 < cr000 ffffh as one-shot pulse output setting the same value to cr000 and cr010 is prohibited. as pulse width measurement using timer output (to00) is prohibited (toc00 = 00h) (2) timer start errors an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because counting tm00 is start ed asynchronously to the count pulse. figure 6-56. start timing of tm00 count 0000h timer start 0001h 0002h 0003h 0004h count pulse tm00 count value (3) setting of cr000 and cr010 (clear & start m ode entered upon a match between tm00 and cr000) set a value other than 0000h to cr000 and cr010 (tm00 c annot count one pulse when it is used as an external event counter). chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 179 (4) timing of holding data by capture register (a) when the valid edge is input to t he ti000/ti010 pin and the reverse phase of the ti000 pin is detected while cr000/cr010 is read, cr010 performs a capture operation but the read value of cr000/cr010 is not guaranteed. at this time, an interrupt signal (inttm 000/inttm010) is generated wh en the valid edge of the ti000/ti010 pin is detected (t he interrupt signal is not generated when the reverse-phase edge of the ti000 pin is detected). when the count value is captured because the valid edge of the ti000/ti010 pi n was detected, read the value of cr000/cr010 after inttm000/inttm010 is generated. figure 6-57. timing of holding data by capture register n n + 1 n + 2 x n + 1 m m + 1 m + 2 count pulse tm00 count value edge input inttm010 value captured to cr010 capture read signal capture operation is performed but read value is not guaranteed. capture operation (b) the values of cr000 and cr010 are not guarant eed after 16-bit timer/event counter 00 stops. (5) setting valid edge set the valid edge of the ti000 pin while the timer operation is stopped (tmc003 and tmc002 = 00). set the valid edge by using es000 and es001. (6) re-triggering one-shot pulse make sure that the trigger is not generated while an active level is being output in t he one-shot pulse output mode. be sure to input the next trigger afte r the current active level is output. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 180 (7) operation of ovf00 flag (a) setting ovf00 flag (1) the ovf00 flag is set to 1 in the following case, as well as when tm00 overflows. select the clear & start mode entered upon a match between tm00 and cr000. set cr000 to ffffh. when tm00 matches cr000 and tm00 is cleared from ffffh to 0000h figure 6-58. operation timing of ovf00 flag fffeh ffffh ffffh 0000h 0001h count pulse tm00 inttm000 ovf00 cr000 (b) clearing ovf00 flag even if the ovf00 flag is cleared to 0 after tm00 overflows and before the next count clock is counted (before the value of tm00 becomes 0001h), it is set to 1 again and clearing is invalid. (8) one-shot pulse output one-shot pulse output operates correct ly in the free-running timer mode or the clear & start mode entered by the ti000 pin valid edge. the one-shot pulse cannot be output in the clea r & start mode entered upon a match between tm00 and cr000. chapter 6 16-bit timer/event counter 00 user?s manual u18685ej3v0ud 181 (9) capture operation (a) when valid edge of ti 000 is specified as count clock when the valid edge of ti000 is specified as the count cl ock, the capture register for which ti000 is specified as a trigger does not operate correctly. (b) pulse width to accurately capture value by signals input to ti010 and ti000 pins to accurately capture the count value, the pulse input to the ti000 and ti010 pins as a capture trigger must be wider than two count clocks selected by prm00 (see figure 6-7 ). (c) generation of interrupt signal the capture operation is per formed at the falling edge of the count clock but the in terrupt signals (inttm000 and inttm010) are generated at the risi ng edge of the next count clock (see figure 6-7 ). (d) note when crc001 (bit 1 of capture/compa re control register 00 (crc00)) is set to 1 when the count value of the tm00 regist er is captured to the cr000 regi ster in the phase reverse to the signal input to the ti000 pin, the interrupt signal (i nttm000) is not generated after the count value is captured. if the valid edge is det ected on the ti010 pin during this oper ation, the captur e operation is not performed but the inttm000 signal is generated as an ex ternal interrupt signal. mask the inttm000 signal when the external interrupt is not used. (10) edge detection (a) specifying valid edge after reset if the operation of the 16-bit timer/ev ent counter 00 is enabled after reset and while the ti000 or ti010 pin is at high level and when the rising edge or both the edges are specified as the valid edge of the ti000 or ti010 pin, then the high level of the ti000 or ti010 pin is detected as the rising edge. note this when the ti000 or ti010 pin is pulled up. however, t he rising edge is not detected when the operation is once stopped and then enabled again. (b) sampling clock for eliminating noise the sampling clock for eliminating noise differs depend ing on whether the valid edge of ti000 is used as the count clock or capture trigger. in the fo rmer case, the sampling clock is fixed to f prs . in the latter, the count clock selected by prm00 is used for sampling. when the signal input to the ti000 pin is sampled and the valid level is detected two times in a row, the valid edge is detected. therefore, noise having a short pulse width can be eliminated (see figure 6-7 ). (11) timer operation the signal input to the ti000/ti010 pin is not acknow ledged while the timer is stopped, regardless of the operation mode of the cpu. remark f prs : peripheral hardware clock frequency user?s manual u18685ej3v0ud 182 chapter 7 8-bit timer/even t counters 50 and 51 7.1 functions of 8-bit ti mer/event counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. ? interval timer ? external event counter ? square-wave output ? pwm output 7.2 configuration of 8-bit timer/event counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. table 7-1. configuration of 8-bit timer/event counters 50 and 51 item configuration timer register 8-bit timer counter 5n (tm5n) register 8-bit timer compare register 5n (cr5n) timer input ti5n timer output to5n control registers timer clock selection register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 0 (pm0) port register 0 (p0) port output mode register 0 (pom0) figures 7-1 and 7-2 show the block diagrams of 8-bit timer/event counters 50 and 51. chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 183 figure 7-1. block diagram of 8-bit timer/event counter 50 internal bus 8-bit timer compare register 50 (cr50) ti50/to50/ p06/intp1 f prs /2 13 f prs f prs /2 match mask circuit ovf 3 clear tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 lvs50 lvr50 tmc501 toe50 invert level 8-bit timer mode control register 50 (tmc50) s r s q r inv selector to tmh0 to uart6 inttm50 to50 output to50/ti50/ p06/intp1 note 1 note 2 selector 8-bit timer counter 50 (tm50) selector f prs /2 2 f prs /2 8 f prs /2 6 output latch (p06) pom06 pm06 figure 7-2. block diagram of 8-bit timer/event counter 51 internal bus 8-bit timer compare register 51 (cr51) ti51/to51/ p00 the carrier clock which was generated in tmh1 f prs f prs /2 match mask circuit ovf 3 clear tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r s q r inv selector inttm51, inttmh1 to51 output to51/ti51/ p00 note 1 note 2 selector 8-bit timer counter 51 (tm51) selector f prs /2 6 f prs /2 4 f prs /2 8 output latch (p00) pom00 pm00 notes 1. timer output f/f 2. pwm output f/f chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 184 (1) 8-bit timer counter 5n (tm5n) tm5n is an 8-bit register that count s the count pulses and is read-only. the counter is incremented in synchronization with the rising edge of the count clock. figure 7-3. format of 8-bit timer counter 5n (tm5n) symbol tm5n (n = 0, 1) address: ff16h (tm50), ff1fh (tm51) after reset: 00h r in the following situations, the count value is cleared to 00h. <1> reset signal generation <2> when tce5n is cleared <3> when tm5n and cr5n match in the mode in which clear & start occurs upon a match of the tm5n and cr5n. (2) 8-bit timer compare register 5n (cr5n) cr5n can be read and written by an 8-bi t memory manipulation instruction. except in pwm mode, the value set in cr5n is constantly compared with the 8-bit timer counter 5n (tm5n) count value, and an interrupt request (in ttm5n) is generated if they match. in the pwm mode, to5n output becomes inactive when the values of tm5n and cr5n ma tch, but no interrupt is generated. the value of cr5n can be set within 00h to ffh. reset signal generation clears cr5n to 00h. figure 7-4. format of 8-bit time r compare register 5n (cr5n) symbol cr5n (n = 0, 1) address: ff17h (cr50), ff41h (cr51) after reset: 00h r/w cautions 1. in the mode in which clear & start oc curs on a match of tm5n and cr5n (tmc5n6 = 0), do not write other values to cr5n during operation. 2. in pwm mode, make the cr5n rewrite peri od 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 185 7.3 registers controlling 8-bit ti mer/event counters 50 and 51 the following four registers are used to co ntrol 8-bit timer/event counters 50 and 51. ? timer clock selection register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) ? port mode register 0 (pm0) ? port register 0 (p0) ? port output mode register 0 (pom0) (1) timer clock selecti on register 5n (tcl5n) this register sets the count clock of 8-bit timer/ev ent counter 5n and the valid edge of the ti5n pin input. tcl5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears tcl5n to 00h. remark n = 0, 1 figure 7-5. format of timer clo ck selection register 50 (tcl50) address: ff6ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl50 0 0 0 0 0 tcl502 tcl501 tcl500 count clock selection tcl502 tcl501 tcl500 f prs = 2 mhz f prs = 4 mhz 0 0 0 ti50 pin falling edge 0 0 1 ti50 pin rising edge 0 1 0 f prs 2 mhz 4 mhz 0 1 1 f prs /2 1 mhz 2 mhz 1 0 0 f prs /2 2 500 khz 1 mhz 1 0 1 f prs /2 6 31.25 khz 62.25 khz 1 1 0 f prs /2 8 7.81 khz 15.6 khz 1 1 1 f prs /2 13 0.24 khz 0.488 khz cautions 1. when rewriting tcl50 to othe r data, stop the timer operation beforehand. 2. be sure to clear bits 3 to 7 to ?0?. remark f prs : peripheral hardware clock frequency chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 186 figure 7-6. format of timer clo ck selection register 51 (tcl51) address: ff8ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl51 0 0 0 0 0 tcl512 tcl511 tcl510 count clock selection tcl512 tcl511 tcl510 f prs = 2 mhz f prs = 4 mhz 0 0 0 ti51 pin falling edge 0 0 1 ti51 pin rising edge 0 1 0 f prs 2 mhz 4mhz 0 1 1 f prs /2 1 mhz 2mhz 1 0 0 f prs /2 4 125 khz 250 khz 1 0 1 f prs /2 6 31.25 khz 62.5 khz 1 1 0 f prs /2 8 7.81 khz 15.6 khz 1 1 1 the carrier clock which was generated in tmh1 ? ? cautions 1. when rewriting tcl51 to othe r data, stop the timer operation beforehand. 2. be sure to clear bits 3 to 7 to ?0?. remark f prs : peripheral hardware clock frequency chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 187 (2) 8-bit timer mode control register 5n (tmc5n) tmc5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (tm5n) count operation control <2> 8-bit timer counter 5n (tm5n) operating mode selection <3> timer output f/f (flip flop) status setting <4> active level selection in timer f/f control or pwm (free-running) mode. <5> timer output control tmc5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark n = 0, 1 figure 7-7. format of 8-bit timer mode control register 50 (tmc50) address: ff6bh after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc506 tm50 operating mode selection 0 mode in which clear & start occurs on a match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f clear (0) (default value of to50 output: low level) 1 0 timer output f/f set (1) (defaul t value of to50 output: high level) 1 1 setting prohibited in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) tmc501 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe50 timer output control 0 output disabled (to50 output is low level) 1 output enabled note bits 2 and 3 are write-only. ( cautions and remarks are listed on the next page.) chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 188 figure 7-8. format of 8-bit timer mode control register 51 (tmc51) address: ff43h after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc51 tce51 tmc516 0 0 lvs51 lvr51 tmc511 toe51 tce51 tm51 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc516 tm51 operating mode selection 0 mode in which clear & start occurs on a match between tm51 and cr51 1 pwm (free-running) mode lvs51 lvr51 timer output f/f status setting 0 0 no change 0 1 timer output f/f clear (0) (default value of to51 output: low level) 1 0 timer output f/f set (1) (defaul t value of to51 output: high level) 1 1 setting prohibited in other modes (tmc516 = 0) in pwm mode (tmc516 = 1) tmc511 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe51 timer output control 0 output disabled (to51 output is low level) 1 output enabled note bits 2 and 3 are write-only. cautions 1. the settings of lvs5n and lv r5n are valid in other than pwm mode. 2. perform <1> to <4> below in the following order, not at the same time. <1> set tmc5n1, tmc5n6 : operation mode setting <2> set toe5n to enable output: timer output enable <3> set lvs5n, lvr5n (see caution 1): timer f/f setting <4> set tce5n 3. when tce5n = 1, setting the ot her bits of tmc5n is prohibited. 4. the actual to50/ti50/p06/intp1 and to51/ti 51/p00 pin outputs are determined depending on pm06 and p06, and pm00 and p00, besides to5n output. remarks 1. in pwm mode, pwm output is made inactive by clearing tce5n to 0. 2. if lvs5n and lvr5n are read, the value is 0. 3. the values of the tmc5n6, l vs5n, lvr5n, tmc5n1, and toe5n bi ts are reflected in to5n output regardless of the value of tce5n. 4. n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 189 (3) port mode registers 0 (pm0) this register set port 0 input/output in 1-bit units. when using the p06/to50/ti50/intp1 and p00/to51/ti51 pins for timer output, clear pm06 and pm00 and the output latches of p06 and p00 to 0. when using the p06/to50/ti50/intp1 an d p00/to51/ti51 pins for timer input, set pm06 and pm00 to 1. the output latches of p06 and p00 at this time may be 0 or 1. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 7-9. format of port mode register 0 (pm0) address: ff20h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm0 pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0n p0n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) (4) port output mode resistors (pom0) this register set the output mode of port 0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to 00h. figure 7-10. format of pull-up resistor option register 7 pom07 symbol pom0 6 pom06 5 pom05 4 pom04 3 pom03 2 pom02 1 pom01 0 pom00 address ff38h after reset 00h r/w r/w pom0n p0n pin output mode selection (n = 0 to 7) 0 cmos output 1 n-ch open-drain output (p07:p-ch open-drain output) chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 190 7.4 operations of 8-bit timer/event counters 50 and 51 7.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval time r that generates interrupt req uests repeatedly at intervals of the count value preset to 8-bi t timer compare register 5n (cr5n). when the count value of 8-bit timer counter 5n (tm5n) ma tches the value set to cr5n, counting continues with the tm5n value cleared to 0 and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). setting <1> set the registers. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, se lect the mode in which clear & start occurs on a match of tm5n and cr5n. (tmc5n = 0000 0b = don?t care) <2> after tce5n = 1 is set, the count operation starts. <3> if the values of tm5n and cr5n match, intt m5n is generated (tm5n is cleared to 00h). <4> inttm5n is generated repeatedly at the same interval. set tce5n to 0 to stop the count operation. caution do not write other values to cr5n during operation. remarks 1. for how to enable the inttm5n signal interrupt, see chapter 11 interrupt functions . 2. n = 0, 1 figure 7-11. interval ti mer operation timing (1/2) (a) basic operation t count clock tm5n count value cr5n tce5n inttm5n count start clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt acknowledged interrupt acknowledged interval time interval time remark interval time = (n + 1) t n = 01h to ffh n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 191 figure 7-11. interval ti mer operation timing (2/2) (b) when cr5n = 00h t interval time count clock tm5n cr5n tce5n inttm5n 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n 01h feh ffh 00h feh ffh 00h ffh ffh ffh interval time interrupt acknowledged interrupt acknowledged remark n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 192 7.4.2 operation as external event counter the external event counter c ounts the number of external clock pulses to be input to the ti5n pin by 8-bit timer counter 5n (tm5n). tm5n is incremented each time the valid edge specified by timer clock selection regist er 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n count value matches the value of 8-bit ti mer compare register 5n (cr5n), tm5n is cleared to 0 and an interrupt request signal (inttm5n) is generated. whenever the tm5n value matches the va lue of cr5n, inttm5n is generated. setting <1> set each register. ? set the port mode register (pm06 or pm00) note to 1. ? tcl5n: select ti5n pin input edge. ti5n pin falling edge tcl5n = 00h ti5n pin rising edge tcl5n = 01h ? cr5n: compare value ? tmc5n: stop the count operation, select the mode in which clear & start occurs on match of tm5n and cr5n, disable the timer f/f inversion operation, disable timer output. (tmc5n = 00000000b) <2> when tce5n = 1 is set, the number of pu lses input from the ti5n pin is counted. <3> when the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> after these settings, inttm5n is generated each time the values of tm5n and cr5n match. note 8-bit timer/event counter 50: pm06 8-bit timer/event counter 51: pm00 remark for how to enable the inttm5n signal interrupt, see chapter 11 interrupt functions . figure 7-12. external event counter oper ation timing (with rising edge specified) ti5n tm5n count value cr5n inttm5n 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n count start remark n = 00h to ffh n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 193 7.4.3 square-wave output operation a square wave with any selected frequency is output at in tervals determined by the value preset to 8-bit timer compare register 5n (cr5n). the to5n output status is in verted at intervals determined by the count value preset to cr5n by setting bit 0 (toe5n) of 8-bit timer mode control r egister 5n (tmc5n) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). setting <1> set each register. ? clear the port output latch (p06 or p00) note and port mode register (pm06 or pm00) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operat ion, select the mode in which clear & start occurs on a match of tm5n and cr5n. lvs5n lvr5n timer output f/f status setting 0 1 timer output f/f clear (0) (default value of to5n output: low level) 1 0 timer output f/f set (1) (defaul t value of to5n output: high level) timer output enabled (tmc5n = 00001011b or 00000111b) <2> after tce5n = 1 is set, the count operation starts. <3> the timer output f/f is inverted by a match of tm5n and cr5n. after inttm5n is generated, tm5n is cleared to 00h. <4> after these settings, the timer output f/f is inverted at the same interval and a square wave is output from to5n. the frequency is as follows. ? frequency = 1/2t (n + 1) (n: 00h to ffh) note 8-bit timer/event counter 50: p06, pm06 8-bit timer/event counter 51: p00, pm00 caution do not write other values to cr5n during operation. remarks 1. for how to enable the inttm5n signal interrupt, see chapter 11 interrupt functions . 2. n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 194 figure 7-13. square-wave output operation timing count clock tm5n count value 00h 01h 02h n ? 1n n 00h n ? 1 n 00h 01h 02h cr5n to5n note t count start note the initial value of to5n output c an be set by bits 2 and 3 (lvr5n, lvs5n) of 8-bit timer mode control register 5n (tmc5n). 7.4.4 pwm output operation 8-bit timer/event counter 5n operates as a pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. the duty pulse determined by the value set to 8-bit time r compare register 5n (cr5n) is output from to5n. set the active level width of the pwm pulse to cr5n; the active level can be selected with bit 1 (tmc5n1) of tmc5n. the count clock can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). pwm output can be enabled/disabled with bit 0 (toe5n) of tmc5n. caution in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 195 (1) pwm output basic operation setting <1> set each register. ? clear the port output latch (p06 or p00) note and port mode register (pm06 or pm00) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, select pwm mode. the timer output f/f is not changed. tmc5n1 active level selection 0 active-high 1 active-low timer output enabled (tmc5n = 01000001b or 01000011b) <2> the count operation starts when tce5n = 1. clear tce5n to 0 to stop the count operation. note 8-bit timer/event counter 50: p06, pm06 8-bit timer/event counter 51: p00, pm00 pwm output operation <1> pwm output (to5n output) outputs an inactive level until an overflow occurs. <2> when an overflow occurs, the active level is output. the active level is output until cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> after the cr5n matches the count value, the inacti ve level is output until an overflow occurs again. <4> operations <2> and <3> are repe ated until the count operation stops. <5> when the count operation is stopped with tce5n = 0, pwm output becomes inactive. for details of timing, see figures 7-14 and 7-15 . the cycle, active-level width, and duty are as follows. ? cycle = 2 8 t ? active-level width = nt ? duty = n/2 8 (n = 00h to ffh) remark n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 196 figure 7-14. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h n <2> active level <1> inactive level <3> inactive level <5> inactive level t <2> active level (b) cr5n = 00h count clock tm5n cr5n tce5n inttm5n 01h 00h ffh 00h 01h 02h 00h ffh 00h 01h 02h m 00h to5n l (inactive level) t (c) cr5n = ffh tm5n cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h ffh <1> inactive level <2> active level ffh 00h 01h 02h m 00h <3> inactive level <2> active level <5> inactive level t remarks 1. <1> to <3> and <5> in figure 7-14 (a) correspond to <1> to <3> and <5> in pwm output operation in 7.4.4 (1) pwm output basic operation . 2. n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 197 (2) operation with cr5n changed figure 7-15. timing of operation with cr5n changed (a) cr5n value is changed from n to m before clock rising edge of ffh value is transferred to cr5n at overflow immediately after change. count clock tm5n cr5n tce5n inttm5n to5n <1> cr5n change (n m) n n + 1 n + 2 ffh 00h 01h m m + 1 m + 2 ffh 00h 01h 02h m m + 1 m + 2 n 02h m h <2> t (b) cr5n value is changed from n to m after clock rising edge of ffh value is transferred to cr5n at second overflow. count clock tm5n cr5n tce5n inttm5n to5n n n + 1 n + 2 ffh 00h 01h n n + 1 n + 2 ffh 00h 01h 02h n 02h n h m m m + 1 m + 2 <1> cr5n change (n m) <2> t caution when reading from cr5n betw een <1> and <2> in figure 7-15, the value read differs from the actual value (read value: m, actual value of cr5n: n). chapter 7 8-bit timer/event counters 50 and 51 user?s manual u18685ej3v0ud 198 7.5 cautions for 8-bit ti mer/event counters 50 and 51 (1) timer start error an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because 8-bit timer counters 50 and 51 (tm50, tm 51) are started asynchronous ly to the count clock. figure 7-16. 8-bit timer counter 5n start timing count clock tm5n count value 00h 01h 02h 03h 04h timer start remark n = 0, 1 user?s manual u18685ej3v0ud 199 chapter 8 8-bit timers h0 and h1 8.1 functions of 8-bit timers h0 and h1 8-bit timers h0 and h1 have the following functions. ? interval timer ? square-wave output ? pwm output ? carrier generator output for remote control (8-bit timer h1 only) 8.2 configuration of 8-bit timers h0 and h1 8-bit timers h0 and h1 include the following hardware. table 8-1. configuration of 8-bit timers h0 and h1 item configuration timer register 8-bit timer counter hn registers 8-bit timer h compare register 0n (cmp0n) 8-bit timer h compare register 1n (cmp1n) timer output toh0, toh1/rem, output controller control registers 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register 1 (tmcyc1) note port mode register 0 (pm0) port register 0 (p0) port output mode register 0 (pm0) note 8-bit timer h1 only remark n = 0, 1 figures 8-1 and 8-2 show the block diagrams. chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 200 figure 8-1. block di agram of 8-bit timer h0 tmhe0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 toh0/p01 toh0 output inttmh0 f prs f prs /2 f prs /2 2 f prs /2 6 f prs /2 10 1 0 f/f r 3 2 pm01 match internal bus 8-bit timer h mode register 0 (tmhmd0) 8-bit timer h compare register 10 (cmp10) decoder selector interrupt generator output controller level inversion pwm mode signal timer h enable signal clear 8-bit timer h compare register 00 (cmp00) output latch (p01) 8-bit timer/ event counter 50 output selector 8-bit timer counter h0 pom01 chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 201 figure 8-2. block di agram of 8-bit timer h1 match internal bus tmhe1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 8-bit timer h compare register 1 1 (cmp11) decoder toh1/ rem/ p07 8-bit timer h carrier control register 1 (tmcyc1) inttmh1 inttm51 toh1 output selector f prs f prs /2 2 f prs /2 4 f prs /2 6 f prs /2 12 f rl f rl /2 7 2f prs interrupt generator output controller level inversion output latch (p16) 1 0 f/f r pwm mode signal carrier generator mode signal timer h enable signal 3 2 8-bit timer h compare register 0 1 (cmp01) 8-bit timer counter h1 clear rmc1 nrzb1 nrz1 reload/ interrupt control 8-bit timer h mode register 1 (tmhmd1) selector pm07 pom07 carrier clock count clock of tm51 chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 202 (1) 8-bit timer h compar e register 0n (cmp0n) this register can be read or written by an 8-bit memory mani pulation instruction. this r egister is used in all of the timer operation modes. this register constantly compares t he value set to cmp0n with the count value of 8-bit timer counter hn and, when the two values match, generates an interrupt request signal (inttm hn) and inverts the output level of tohn. rewrite the value of cmp0n while the timer is stopped (tmhen = 0). a reset signal generation clears this register to 00h. figure 8-3. format of 8-bit time r h compare register 0n (cmp0n) symbol cmp0n (n = 0, 1) address: ff18h (cmp00), ff1ah (cmp01) after reset: 00h r/w 7 6 5 4 32 1 0 caution cmp0n cannot be rewritten during timer count operation. cmp0n can be refreshed (the same value is written) during timer count operation. (2) 8-bit timer h compar e register 1n (cmp1n) this register can be read or written by an 8-bit memory manipulation instruction. this register is used in the pwm output mode and carrier generator mode. in the pwm output mode, this register constantly compares the value set to cmp1n with the count value of 8-bit timer counter hn and, when the two values match, inverts the output level of tohn. no interrupt request signal is generated. in the carrier generator mode, the cm p1n register always compares the val ue set to cmp1n with the count value of 8-bit timer counter hn and, when the two values match, generates an interrupt request signal (inttmhn). at the same time, the count value is cleared. cmp1n can be refreshed (the same value is writt en) and rewritten during timer count operation. if the value of cmp1n is rewritten while the timer is oper ating, the new value is la tched and transferred to cmp1n when the count value of the timer matches the old val ue of cmp1n, and then the valu e of cmp1n is changed to the new value. if matching of the count value and the cmp1n value and wr iting a value to cmp1n conflict, the value of cmp1n is not changed. a reset signal generation clears this register to 00h. figure 8-4. format of 8-bit time r h compare register 1n (cmp1n) symbol cmp1n (n = 0, 1) address: ff19h (cmp10), ff1bh (cmp11) after reset: 00h r/w 7 6 5 4 32 1 0 caution in the pwm output mode and carrier genera tor mode, be sure to set cmp1n when starting the timer count operation (tmhen = 1) after the ti mer count operation was stopped (tmhen = 0) (be sure to set again even if se tting the same value to cmp1n). remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 203 8.3 registers controlling 8-bit timers h0 and h1 the following four registers are used to control 8-bit timers h0 and h1. ? 8-bit timer h mode register n (tmhmdn) ? 8-bit timer h carrier control register 1 (tmcyc1) note ? port mode register 0 (pm0) ? port register 0 (p0) ? port mode register 0 (pm0) note 8-bit timer h1 only (1) 8-bit timer h mode register n (tmhmdn) this register controls the mode of timer h. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 204 figure 8-5. format of 8-bit timer h mode register 0 (tmhmd0) tmhe0 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe0 0 1 timer operation enable tmhmd0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 address: ff69h after reset: 00h r/w symbol f prs f prs /2 f prs /2 2 f prs /2 6 f prs /2 10 tm50 output note setting prohibited cks02 0 0 0 0 1 1 cks01 0 0 1 1 0 0 cks00 0 1 0 1 0 1 f prs = 2 mhz 2 mhz 1 mhz 500 khz 31.25 khz 1.95 khz count clock selection other than above interval timer mode pwm output mode setting prohibited tmmd01 0 1 tmmd00 0 0 timer operation mode low level high level tolev0 0 1 timer output level control (in default mode) disables output enables output toen0 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> f prs = 4 mhz 4 mhz 2 mhz 1 mhz 62.5 khz 3.91 khz note note the following points when select ing the tm50 output as the count clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counter 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit timer/event counter 50 fi rst and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. cautions 1. when tmhe0 = 1, setting the other bits of tmhmd0 is prohibited. however, tmhmd0 can be refreshed (the same va lue is written). chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 205 cautions 2. in the pwm output mode, be sure to set 8-bit timer h compare register 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same value to cmp10). 3. the actual toh0/p01 pin output is determine d depending on pm01 and p01, besides toh0 output. remarks 1. f prs : peripheral hardware clock frequency 2. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 figure 8-6. format of 8-bit timer h mode register 1 (tmhmd1) tmhe1 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe1 0 1 timer operation enable tmhmd1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 address: ff6ch after reset: 00h r/w symbol interval timer mode carrier generator mode pwm output mode setting prohibited tmmd11 0 0 1 1 tmmd10 0 1 0 1 timer operation mode low level high level tolev1 0 1 timer output level control (in default mode) disables output enables output toen1 0 1 timer output control <7> 6 5 4 3 2 <1> <0> f prs f prs /2 2 f prs /2 4 f prs /2 6 f prs /2 12 f rl /2 7 2 prs f rl cks12 0 0 0 0 1 1 1 1 cks11 0 0 1 1 0 0 1 1 cks10 0 1 0 1 0 1 0 1 f prs = 2 mhz 2 mhz 500 khz 125 khz 31.25 khz 0.49 khz 1.80 khz (typ.) 4 khz 240 khz (typ.) count clock selection f prs = 4 mhz 4 mhz 1 mhz 250 khz 62.5 khz 0.98 khz 8 mhz chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 206 cautions 1. when tmhe1 = 1, setting the other bits of tmhmd1 is prohibited. however, tmhmd1 can be refreshed (the same va lue is written). 2. in the pwm output mode and carrier generato r mode, be sure to set the 8-bit timer h compare register 11 (cmp11) when star ting the timer count operation (tmh e1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to cmp11). 3. when the carrier generator mode is used, set so that the count clock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. 4. the actual toh1/rem/p07 pin output is de termined depending on pm07 and p07, besides toh1 output. remarks 1. f prs : peripheral hardware clock frequency 2. f rl : internal low-speed oscillation clock frequency (2) 8-bit timer h carrier control register 1 (tmcyc1) this register controls the remote control output and carrier pulse output status of 8-bit timer h1. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 8-7. format of 8-bit timer h carrier control register 1 (tmcyc1) 0 tmcyc1 0 0 0 0 rmc1 nrzb1 nrz1 address: ff6dh after reset: 00h r/w note symbol low-level output high-level output at rising edge of inttm51 signal input low-level output carrier pulse output at rising edge of inttm51 signal input rmc1 0 0 1 1 nrzb1 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enabled status (rmc1 = 1: carrier pulse output, rmc1 = 0: high-level status) nrz1 0 1 carrier pulse output status flag <0> note bit 0 is read-only. caution do not rewrite rmc1 when tmhe = 1. ho wever, tmcyc1 can be refreshed (the same value is written). chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 207 (3) port mode register 0 (pm0) this register sets port 1 input/output in 1-bit units. when using the p01/toh0 and p07/toh1/rem pins for timer output, and carrier generator output for remote control, clear pm01 and pm07 and the ou tput latches of p01 and p07 to 0. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 8-8. format of port mode register 1 (pm0) address: ff20h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm0 pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0n p0n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) (4) port output mode resistors (pom0) this register set the output mode of port 0. set pom07 to 1 when usi ng the p07/toh1/rem pin for carrier generator output for remote control. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to 00h. figure 8-9. format of pull-up resistor option register 7 pom07 symbol pom0 6 pom06 5 pom05 4 pom04 3 pom03 2 pom02 1 pom01 0 pom00 address ff38h after reset 00h r/w r/w pom0n p0n pin output mode selection (n = 0 to 7) 0 cmos output 1 n-ch open-drain output (p07:p-ch open-drain output) chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 208 8.4 operation of 8-bit timers h0 and h1 8.4.1 operation as inter val timer/square-wave output when 8-bit timer counter hn and compare register 0n (cmp0n) match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. compare register 1n (cmp1n) is not used in interval time r mode. since a match of 8-bit timer counter hn and the cmp1n register is not detected even if the cmp1n register is set, timer output is not affected. by setting bit 0 (toenn) of timer h mode register n (tmh mdn) to 1, a square wave of any frequency (duty = 50%) is output from tohn. setting <1> set each register. figure 8-10. register setting during inte rval timer/square-wave output operation (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output setting default setting of timer output level interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp0n register setting the interval time is as follows if n is set as a comparison value. ? interval time = (n +1) / f cnt <2> count operation starts when tmhen = 1. <3> when the values of 8-bit timer counter hn and the cmp0n register match, t he inttmhn signal is generated and 8-bit timer counter hn is cleared to 00h. <4> subsequently, the inttmhn signal is generated at t he same interval. to stop the count operation, clear tmhen to 0. remarks 1. for the setting of the output pin, see 8.3 (3) port mode register 0 (pm0) and (4) port output mode resistors (pom0) . 2. for how to enable the inttmhn signal interrupt, see chapter 11 interrupt functions . 3. n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 209 figure 8-11. timing of interval time r/square-wave output operation (1/2) (a) basic operation (operation when 01h cmp0n feh) 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <3> <1> <1> the count operation is enabled by setting the tmhen bi t to 1. the count clock starts counting no more than 1 clock after the operation is enabled. <2> when the value of the 8-bit timer counter hn matches the value of the cmp0n regist er, the value of the timer counter is cleared, and the level of th e tohn output is inverted. in addition, the inttmhn signal is output at the rising edge of the count clock. <3> if the tmhen bit is cleared to 0 while timer h is oper ating, the inttmhn signal and tohn output are set to the default level. if they are already at the default level before the tmhen bit is cleared to 0, then that level is maintained. remark n = 0, 1 01h n feh chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 210 figure 8-11. timing of interval time r/square-wave output operation (2/2) (b) operation when cmp0n = ffh 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp0n = 00h 00h 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn interval time remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 211 8.4.2 operation as pwm output in pwm output mode, a pulse with an arbi trary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (cmp0n) controls the cycle of timer output (tohn). re writing the cmp0n register during timer operation is prohibited. 8-bit timer compare register 1n (cmp1n) controls the dut y of timer output (tohn). re writing the cmp1n register during timer operation is possible. the operation in pwm output mode is as follows. pwm output (tohn output) output s an active level and 8-bit timer counter hn is cleared to 0 when 8-bit timer counter hn and the cmp0n register match after the timer count is started. pwm out put (tohn output) outputs an inactive level when 8-bit timer counter hn and the cmp1n register match. setting <1> set each register. figure 8-12. register setting in pwm output mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 1 0 0/1 1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output enabled default setting of timer output level pwm output mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp0n register ? compare value (n): cycle setting (iii) setting cmp1n register ? compare value (m): duty setting remarks 1. n = 0, 1 2. 00h cmp1n (m) < cmp0n (n) ffh <2> the count operation starts when tmhen = 1. <3> the cmp0n register is the compare re gister that is to be compared first after counter operation is enabled. when the values of 8-bit timer counter hn and the cmp0n register match, 8-bit timer counter hn is cleared, an interrupt request signal (inttmhn) is generated, and an active level is output. at the same time, the compare register to be compared with 8-bit timer count er hn is changed from the cmp0n register to the cmp1n register. <4> when 8-bit timer counter hn and the cmp1n register match, an inactive level is output and the compare register to be compared with 8-bit timer counter hn is changed from the cmp1n register to the cmp0n register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 212 <5> by performing procedures <3> and <4> repeatedl y, a pulse with an arbitrary duty can be obtained. <6> to stop the count operation, set tmhen = 0. if the setting value of the cmp0n regist er is n, the setting value of the cmp1n register is m, and the count clock frequency is f cnt , the pwm pulse output cycle and duty are as follows. ? pwm pulse output cycle = (n + 1) / f cnt ? duty = (m + 1) / (n + 1) cautions 1. the set value of the cmp1n register ca n be changed while the time r counter is operating. however, this takes a duration of three operati ng clocks (signal selected by the cksn2 to cksn0 bits of the tmhmdn register) from when the value of the cmp1n register is changed until the value is transferred to the register. 2. be sure to set the cmp1n register when st arting the timer count opera tion (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register). 3. make sure that the cmp1n re gister setting value (m) and cmp0 n register setting value (n) are within the following range. 00h cmp1n (m) < cmp0n (n) ffh remarks 1. for the setting of the output pin, see 8.3 (3) port mode register 0 (pm0) and (4) port output mode resistors (pom0) . 2. for details on how to enable the inttmhn signal interrupt, see chapter 11 interrupt functions . 3. n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 213 figure 8-13. operation timing in pwm output mode (1/4) (a) basic operation count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h cmp1n a5h 01h <1> <2> <3> <4> <1> the count operation is enabled by setting the tmhen bit to 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, pwm output outputs an inactive level. <2> when the values of 8-bit timer count er hn and the cmp0n register match, an active level is output. at this time, the value of 8-bit timer counter hn is cleared, and the inttmhn signal is output. <3> when the values of 8-bit timer count er hn and the cmp1n register match, an inactive level is output. at this time, the 8-bit counter value is not cleared and the inttmhn signal is not output. <4> clearing the tmhen bit to 0 during timer hn operat ion sets the inttmhn signal to the default and pwm output to an inactive level. remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 214 figure 8-13. operation timing in pwm output mode (2/4) (b) operation when cmp0n = ffh, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp1n ffh 00h (c) operation when cmp0n = ffh, cmp1n = feh count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp1n ffh feh remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 215 figure 8-13. operation timing in pwm output mode (3/4) (d) operation when cmp0n = 01h, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp1n 00h remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 216 figure 8-13. operation timing in pwm output mode (4/4) (e) operation by changi ng cmp1n (cmp1n = 02h 03h, cmp0n = a5h) count clock 8-bit timer counter hn cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h <1> <4> <3> <2> cmp11 <6> <5> 02h a5h 03h 02h (03h) <2>? 80h <1> the count operation is enabled by setting tmhen = 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, pwm output outputs an inactive level. <2> the cmp1n register value can be changed during timer counter operation. this operation is asynchronous to the count clock. <3> when the values of 8-bit timer count er hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, an active level is output, and the inttmhn signal is output. <4> if the cmp1n register value is changed, the value is latched and not transferred to the register. when the values of 8-bit timer counter hn and the cmp1n register before the change match, the value is transferred to the cmp1n register and the cmp1n re gister value is changed (<2>?). however, three count clocks or more are required fr om when the cmp1n register value is changed to when the value is transferred to the register. if a match signal is generated within thr ee count clocks, the changed value cannot be transferred to the register. <5> when the values of 8-bit timer counter hn and the cm p1n register after the change match, an inactive level is output. 8-bit timer counter hn is not cl eared and the inttmhn signal is not generated. <6> clearing the tmhen bit to 0 during timer hn operat ion sets the inttmhn signal to the default and pwm output to an inactive level. remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 217 8.4.3 carrier generator opera tion (8-bit timer h1 only) in the carrier generator mode, 8-bit timer h1 is used to generate the carrier signal of an infrared remote controller, and 8-bit timer/event counter 51 is used to generat e an infrared remote control signal (time count). the carrier clock generated by 8-bit timer h1 is output in the cycle set by 8-bit timer/event counter 51. in carrier generator mode, the output of the 8-bit timer h1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the rem output. (1) carrier generation in carrier generator mode, 8-bit timer h compare regist er 01 (cmp01) generates a low-level width carrier pulse waveform and 8-bit timer h compare register 11 (cmp11) generates a high-level width carrier pulse waveform. rewriting the cmp11 register during t he 8-bit timer h1 operation is possible but rewriting the cm p01 register is prohibited. (2) carrier output control carrier output is controlled by the interrupt request sig nal (inttm51) of 8-bit timer/event counter 51 and the nrzb1 and rmc1 bits of the 8-bit timer h carrier contro l register 1 (tmcyc1). the relationship between the outputs is shown below. rmc1 bit nrzb1 bit output 0 0 low-level output 0 1 high-level output at rising edge of inttm51 signal input 1 0 low-level output 1 1 carrier pulse output at rising edge of inttm51 signal input chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 218 to control the carrier pulse output during a count operation, the nrz1 and nrzb1 bits of the tmcyc1 register have a master and slave bit configuratio n. the nrz1 bit is read-only but t he nrzb1 bit can be read and written. the inttm51 signal is synchronized with the 8-bit timer h1 count clock and is output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal of the nrz1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. the timing for transfer from the nrz b1 bit to the nrz1 bit is as shown below. figure 8-14. transfer timing 8-bit timer h1 count clock tmhe1 inttm51 inttm5h1 nrz1 nrzb1 rmc1 1 1 1 0 00 <1> <2> <3> <1> the inttm51 signal is synchronized with the count cl ock of 8-bit timer h1 and is output as the inttm5h1 signal. <2> the value of the nrzb1 bit is tr ansferred to the nrz1 bit at the second clock from the rising edge of the inttm5h1 signal. <3> write the next value to the nrzb1 bit in the inte rrupt servicing program t hat has been started by the inttm5h1 interrupt or after timing has been checked by polling the interrupt request flag. write data to count the next time to the cr51 register. cautions 1. do not rewrite the nrzb1 bit again until at least the second clock afte r it has been rewritten, or else the transfer from the nrzb1 bi t to the nrz1 bit is not guaranteed. 2. when 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. when 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timi ng of the interrupt generation differs. remark inttm5h1 is an internal signal and not an interrupt source. chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 219 setting <1> set each register. figure 8-15. register setting in carrier generator mode (i) setting 8-bit timer h m ode register 1 (tmhmd1) 0 0/1 0/1 0/1 0 timer output enabled default setting of timer output level carrier generator mode selection count clock (f cnt ) selection count operation stopped 1 0/1 1 tmmd10 tolev1 toen1 cks11 cks12 tmhe1 tmhmd1 cks10 tmmd11 (ii) cmp01 register setting ? compare value (iii) cmp11 register setting ? compare value (iv) tmcyc1 register setting ? rmc1 = 1 ... remote control output enable bit ? nrzb1 = 0/1 ... carrier output enable bit (v) tcl51 and tmc51 register setting ? see 7.3 registers controlling 8-bit timer/event counters 50 and 51 . <2> when tmhe1 = 1, 8-bit timer h1 starts counting. <3> when tce51 of 8-bit timer mode control register 51 (tmc 51) is set to 1, 8-bit timer/event counter 51 starts counting. <4> after the count operation is enabled, the first compar e register to be compared is the cmp01 register. when the count value of 8-bit timer counter h1 and t he cmp01 register value match, the inttmh1 signal is generated, 8-bit timer co unter h1 is cleared. at the same time, the compare register to be compared with 8-bit timer counter h1 is switched from t he cmp01 register to the cmp11 register. <5> when the count value of 8-bit timer counter h1 and the cmp11 register value match, the inttmh1 signal is generated, 8-bit timer co unter h1 is cleared. at the same time, the compare register to be compared with 8-bit timer counter h1 is switched from t he cmp11 register to the cmp01 register. <6> by performing procedures <4> and <5> r epeatedly, a carrier clock is generated. <7> the inttm51 signal is synchronized with count clock of 8-bit timer h1 and output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <8> write the next value to the nrzb1 bit in the inte rrupt servicing program that has been started by the inttm5h1 interrupt or after timing has been checked by polling the interrupt request flag. write data to count the next time to the cr51 register. <9> when the nrz1 bit is high level, a carrier clock is output by rem output. chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 220 <10> by performing the procedures above, an arbitrary carrier clock is obtained. to stop the count operation, clear tmhe1 to 0. if the setting value of the cmp01 regist er is n, the setting value of the cmp11 register is m, and the count clock frequency is f cnt , the carrier clock output cycle and duty are as follows. ? carrier clock output cycle = (n + m + 2) / f cnt ? duty = high-level width/carrier clo ck output width = (m + 1) / (n + m + 2) cautions 1. be sure to set the cmp11 register when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmh e1 = 0) (be sure to set again even if setting the same value to the cmp11 register). 2. set so that the count clock frequency of tmh1 becomes more th an 6 times the count clock frequency of tm51. 3. set the values of the cmp01 and cmp 11 registers in a range of 01h to ffh. 4. the set value of the cmp11 register can be changed while the timer counter is operating. however, it takes the duration of three operating clocks (signal selected by the cks12 to cks10 bits of the tmhmd1 re gister) since the val ue of the cmp11 register has been changed until the val ue is transferred to the register. 5. be sure to set the rmc1 bit be fore the count operation is started. remarks 1. for the setting of the output pin, see 8.3 (3) port mode register 0 (pm0) and (4) port output mode resistors (pom0) . 2. for how to enable the inttmh1 signal interrupt, see chapter 11 interrupt functions . chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 221 figure 8-16. carrier generator mode operation timing (1/3) (a) operation when cmp01 = n, cmp11 = n cmp01 cmp11 tmhe11 inttmh1 carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 51 count clock tm51 count value cr5 1 tce5 1 rem 0 0 1 1 0 0 1 1 0 0 inttm5 1 nrzb 1 nrz 1 carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5h 1 <1><2> <3> <4> <5> <6> <7> 8-bit timer h1 count clock 8-bit timer counter h1 count value k l m n <1> when tmhe1 = 0 and tce51 = 0, 8-bit timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, 8-bit timer counter h1 starts a count operation. at that time, the carrier clock remains default. <3> when the count value of 8-bit timer counter h1 matc hes the cmp01 register val ue, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. 8-bit timer counter h1 is cleared to 00h. <4> when the count value of 8-bit timer counter h1 matc hes the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and t he compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with the 8-bit timer h1 count clock and is output as the inttm5h1 signal. <6> the inttm5h1 signal becomes the data transfer si gnal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <7> when nrz1 = 0 is set, the rem output becomes low level. remark inttm5h1 is an internal signal and not an interrupt source. chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 222 figure 8-16. carrier generator mode operation timing (2/3) (b) operation when cmp01 = n, cmp11 = m n cmp01 cmp11 tmhe1 inttmh1 carrier clock tm51 count value 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m tce51 rem 0 0 1 1 0 0 1 1 0 0 inttm51 nrzb1 nrz1 carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5h1 <1><2> <3> <4> <5> <6> <7> 8-bit timer 51 count clock 8-bit timer h1 count clock 8-bit timer counter h1 count value k cr51 l m n <1> when tmhe1 = 0 and tce51 = 0, 8-bit timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, 8-bit timer counter h1 starts a count operation. at that time, the carrier clock remains default. <3> when the count value of 8-bit timer counter h1 matc hes the cmp01 register val ue, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. 8-bit timer counter h1 is cleared to 00h. <4> when the count value of 8-bit timer counter h1 matc hes the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and t he compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with the 8-bit timer h1 count clock and is output as the inttm5h1 signal. <6> a carrier signal is output at the first rising edge of the carrier clock if nrz1 is set to 1. <7> when nrz1 = 0, the rem output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed). remark inttm5h1 is an internal signal and not an interrupt source. chapter 8 8-bit timers h0 and h1 user?s manual u18685ej3v0ud 223 figure 8-16. carrier generator mode operation timing (3/3) (c) operation when cmp11 is changed 8-bit timer h1 count clock cmp01 tmhe1 inttmh1 carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3>? <4> <3> <2> cmp11 <5> m n l m (l) 8-bit timer counter h1 count value <1> when tmhe1 = 1 is set, 8-bit timer h1 starts a count operation. at that time, the carrier clock remains default. <2> when the count value of 8-bit timer counter h1 ma tches the value of the cmp01 register, the inttmh1 signal is output, the carrier signal is inverted, and the ti mer counter is cleared to 00h. at the same time, the compare register whose value is to be compared with that of 8-bit timer counter h1 is changed from the cmp01 register to the cmp11 register. <3> the cmp11 register is asynchronous to the count clock, and its value c an be changed while 8-bit timer h1 is operating. the new value (l) to which the value of the register is to be changed is latched. when the count value of 8-bit timer counter h1 matches the value (m) of the cmp11 register bef ore the change, the cmp11 register is changed (<3>?). however, it takes three count clo cks or more since the value of the cmp11 register ha s been changed until the value is transferred to the regist er. even if a match signal is generat ed before the duration of three count clocks elapses, the new value is not transferred to the register. <4> when the count value of 8-bit timer counter h1 ma tches the value (m) of the cmp1 register before the change, the inttmh1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00h. at the same time, the compare register whose value is to be compared with that of 8-bit timer counter h1 is changed from the cmp11 regist er to the cmp01 register. <5> the timing at which the count value of 8-bit timer counter h1 and the cmp11 regi ster value match again is indicated by the value after the change (l). user?s manual u18685ej3v0ud 224 chapter 9 watchdog timer 9.1 functions of watchdog timer the watchdog timer operates on the internal low-speed oscillation clock. the watchdog timer is used to detect an inadvertent program loop. if a program loop is detected, an internal reset signal is generated. program loop is detected in the following cases. ? if the watchdog timer counter overflows ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if data is written to wdte during a window close period ? if the instruction is fetched from an area not set by the ims register (detection of an invalid check while the cpu hangs up) ? if the cpu accesses an area that is not set by the im s register (excluding fb00h to ffffh) by executing a read/write instruction (detec tion of an abnormal access during a cpu program loop) when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 14 reset function . chapter 9 watchdog timer user?s manual u18685ej3v0ud 225 9.2 configuration of watchdog timer the watchdog timer includes the following hardware. table 9-1. configuration of watchdog timer item configuration control register watchdog timer enable register (wdte) how the counter operation is controlled, overflow ti me, and window open period are set by the option byte. table 9-2. setting of option bytes and watchdog timer setting of watchdog timer option byte (0080h) window open period bits 6 and 5 (window1, window0) controlling counter operation of watchdog timer bit 4 (wdton) overflow time of watchdog timer bits 3 to 1 (wdcs2 to wdcs0) remark for the option byte, see chapter 17 option byte . figure 9-1. block diagram of watchdog timer f rl /2 clock input controller reset output controller internal reset signal internal bus selector 17-bit counter 2 10 /f rl to 2 17 /f rl watchdog timer enable register (wdte) clear, reset control wdton of option byte (0080h) window1 and window0 of option byte (0080h) count clear signal wdcs2 to wdcs0 of option byte (0080h) overflow signal cpu access signal cpu access error detector window size determination signal chapter 9 watchdog timer user?s manual u18685ej3v0ud 226 9.3 register controlling watchdog timer the watchdog timer is controlled by the watchdog timer enable register (wdte). (1) watchdog timer enable register (wdte) writing ach to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 9ah or 1ah note . figure 9-2. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: ff99h after reset: 9ah/1ah note r/w note the wdte reset value differs depending on the wdto n setting value of the option byte (0080h). to operate watchdog timer, set wdton to 1. wdton setting value wdte reset value 0 (watchdog timer count operation disabled) 1ah 1 (watchdog timer count operation enabled) 9ah cautions 1. if a value other than ach is written to wdte, an internal reset signal is generated. if the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 2. if a 1-bit memory manipulation instructio n is executed for wdte, an internal reset signal is generated. if the source clock to the wa tchdog timer is stopped, however, an internal reset signal is genera ted when the source clock to th e watchdog timer resumes operation. 3. the value read from wdte is 9ah/1ah (this differs fr om the written value (ach)). chapter 9 watchdog timer user?s manual u18685ej3v0ud 227 9.4 operation of watchdog timer 9.4.1 controlling operation of watchdog timer 1. when the watchdog timer is used, its operati on is specified by the option byte (0080h). ? enable counting operation of the watchdog timer by se tting bit 4 (wdton) of the option byte (0080h) to 1 (the counter starts operating after a reset release) (for details, see chapter 17 ). wdton operation control of watchdog ti mer counter/illegal access detection 0 counter operation disabled (counting stopped after rese t), illegal access detection operation disabled 1 counter operation enabled (counting started after reset), illegal access detection operation enabled ? set an overflow time by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (0080h) (for details, see 9.4.2 and chapter 17 ). ? set a window open period by using bits 6 and 5 (wi ndow1 and window0) of the opt ion byte (0080h) (for details, see 9.4.3 and chapter 17 ). 2. after a reset release, the watchdog timer starts counting. 3. by writing ?ach? to wdte after the watchdog timer starts counting and before the overflow time set by the option byte, the watchdog timer is cl eared and starts counting again. 4. after that, write wdte the second time or later afte r a reset release during the window open period. if wdte is written during a window close period, an internal reset signal is generated. 5. if the overflow time expires without ?ach? wri tten to wdte, an internal reset signal is generated. a internal reset signal is generated in the following cases. ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if the instruction is fetched from an area not set by t he ims register (detection of an invalid check during a cpu program loop) ? if the cpu accesses an area not set by the ims r egister (excluding fb00h to ffffh) by executing a read/write instruction (detec tion of an abnormal access during a cpu program loop) cautions 1. the first writing to wdte after a reset releas e clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. 2. if the watchdog timer is cleared by writi ng ?ach? to wdte, the actual overflow time may be different from the overflow time set by the option byte by up to 2/f rl seconds. 3. the watchdog timer can be cleared immediately before the count value overflows (ffffh). chapter 9 watchdog timer user?s manual u18685ej3v0ud 228 cautions 4. the operation of the watchdog time r in the halt and stop modes differs as follows depending on the set value of bit 0 (lsrosc) of the option byte. lsrosc = 0 (internal low-speed oscillator can be stopped by software) lsrosc = 1 (internal low-speed oscillator cannot be stopped) in halt mode in stop mode watchdog timer operation stops. watchdog timer operation continues. if lsrosc = 0, the watchdog timer resu mes counting after the halt or stop mode is released. at this time, the counter is not clear ed to 0 but starts counting from the value at which it was stopped. if oscillation of the internal low-speed osc illator is stopped by setting lsrstop (bit 1 of the internal oscillation mode register (rcm) = 1) when lsrosc = 0, the watchdog timer stops operating. at this time, the counter is not cleared to 0. 5. the watchdog timer continues its operati on during self programming of the flash memory. during processing, the interrupt acknowledge time is delayed. set the overflow time and window size taking this delay into consideration. 9.4.2 setting overflow time of watchdog timer set the overflow time of the watchdog timer by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (0080h). if an overflow occurs, an internal reset signal is generat ed. the present count is cleared and the watchdog timer starts counting again by writing ?ach? to wdte dur ing the window open period before the overflow time. the following overflow time is set. table 9-3. setting of overflow time of watchdog timer (when 2.1 v v dd 3.6 v) wdcs2 wdcs1 wdcs0 overflow time of watchdog timer 0 0 0 2 10 /f rl (3.71 ms) 0 0 1 2 11 /f rl (7.42 ms) 0 1 0 2 12 /f rl (14.84 ms) 0 1 1 2 13 /f rl (29.68 ms) 1 0 0 2 14 /f rl (59.36 ms) 1 0 1 2 15 /f rl (118.72 ms) 1 1 0 2 16 /f rl (237.45 ms) 1 1 1 2 17 /f rl (474.90 ms) cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer continues its ope ration during self programming of the flash memory. during processing, the interrupt acknowledge time is delayed. set the overflow time and window size taki ng this delay into consideration. remarks 1. f rl : internal low-speed oscillation clock frequency 2. ( ): f rl = 276 khz (max.) chapter 9 watchdog timer user?s manual u18685ej3v0ud 229 table 9-4. setting of overflow time of watchdog timer (when 1.8 v v dd < 2.1 v) wdcs2 wdcs1 wdcs0 overflow time of watchdog timer 0 0 0 2 10 /f rl (3.41ms) 0 0 1 2 11 /f rl (6.83 ms) 0 1 0 2 12 /f rl (13.65 ms) 0 1 1 2 13 /f rl (27.31 ms) 1 0 0 2 14 /f rl (54.61 ms) 1 0 1 2 15 /f rl (109.23 ms) 1 1 0 2 16 /f rl (218.45 ms) 1 1 1 2 17 /f rl (436.91 ms) cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer continues its ope ration during self programming of the flash memory. during processing, the interrupt acknowledge time is delayed. set the overflow time and window size taki ng this delay into consideration. remarks 1. f rl : internal low-speed oscillation clock frequency 2. ( ): f rl = 300 khz (max.) 9.4.3 setting window open period of watchdog timer set the window open period of the watchdog timer by usi ng bits 6 and 5 (window1, window0) of the option byte (0080h). the outline of the window is as follows. ? if ?ach? is written to wdte during the window open per iod, the watchdog timer is cleared and starts counting again. ? even if ?ach? is written to wdte during the window cl ose period, an abnormality is detected and an internal reset signal is generated. example : if the window open period is 25% window close period (75%) window open period (25%) counting starts overflow time counting starts again when ach is written to wdte. internal reset signal is generated if ach is written to wdte. caution the first writing to wdte after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of th e writing, and the watc hdog timer starts counting again. the window open period to be set is as follows. chapter 9 watchdog timer user?s manual u18685ej3v0ud 230 table 9-5. setting window op en period of watchdog timer window1 window0 window open period of watchdog timer 0 0 25% 0 1 50% 1 0 75% 1 1 100% cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer continues its ope ration during self programming of the flash memory. during processing, the interrupt acknowledge time is delayed. set the overflow time and window size taki ng this delay into consideration. remark if the overflow time is set to 2 10 /f rl , the window close time and open time are as follows. (when 2.1 v v dd 3.6 v) setting of window open period 25% 50% 75% 100% window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 1.19 ms none window open time 3.56 to 3.71 ms 2.37 to 3.71 ms 1.19 to 3.71 ms 0 to 3.71 ms user?s manual u18685ej3v0ud 231 chapter 10 serial interface uart6 10.1 functions of serial interface uart6 serial interface uart6 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 10.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode the functions of this mode are outlined below. for details, see 10.4.2 asynchronous seri al interface (uart) mode and 10.4.3 dedicated baud rate generator . ? maximum transfer rate: 312.5 kbps ? two-pin configuration t x d6: transmit data output pin r x d6: receive data input pin ? data length of communication data can be selected from 7 or 8 bits. ? dedicated internal 8-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performe d independently (full duplex operation). ? msb- or lsb-first communication selectable ? inverted transmission operation cautions 1. the t x d6 output inversion function inverts only th e transmission side a nd not the reception side. to use this f unction, the reception side must be ready for reception of inverted data. 2. if clock supply to serial interface uart6 is not stopped (e .g., in the halt mode), normal operation continues. if clock supply to serial interface uart6 is stopped (e.g., in the stop mode), each register stops operating, and hold s the value immediatel y before clock supply was stopped. the t x d6 pin also holds the value imme diately before clock supply was stopped and outputs it. however, the operati on is not guaranteed after clock supply is resumed. therefore, reset the circuit so th at power6 = 0, rxe6 = 0, and txe6 = 0. 3. set power6 = 1 and then set txe6 = 1 (tr ansmission) or rxe6 = 1 (reception) to start communication. 4. txe6 and rxe6 are sync hronized by the base clock (f xclk6 ) set by cksr6. to enable transmission or reception again, set txe6 or r xe6 to 1 at least two clocks of the base clock after txe6 or rxe6 has been cleared to 0. if txe6 or rxe6 is set within two clocks of the base clock, the transmission circuit or reception circui t may not be initialized. 5. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. 6. if data is continuously tr ansmitted, the communicat ion timing from the stop bit to the next start bit is extended two operating clocks of the macro. however, th is does not affect the result of communication because the reception side initializ es the timing when it has detected a start bit. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 232 10.2 configuration of serial interface uart6 serial interface uart6 includes the following hardware. table 10-1. configurati on of serial interface uart6 item configuration registers receive buffer register 6 (rxb6) receive shift register 6 (rxs6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) control registers asynchronous serial interface o peration mode register 6 (asim6) asynchronous serial interface recepti on error status register 6 (asis6) asynchronous serial interface transm ission status register 6 (asif6) clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) asynchronous serial interface control register 6 (asicl6) port mode register 0 (pm0) port register 0 (p0) port output mode register 0 (pom0) chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 233 figure 10-1. block diagram of serial interface uart6 internal bus asynchronous serial interface control register 6 (asicl6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) t x d6/ p02/ ti000 intst6 baud rate generator asynchronous serial interface control register 6 (asicl6) reception control receive shift register 6 (rxs6) receive buffer register 6 (rxb6) r x d6/p03/ ti010/to00 intsr6 baud rate generator filter intsre6 asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface transmission status register 6 (asif6) transmission control registers f prs f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 f prs /2 8 f prs /2 9 f prs /2 10 8-bit timer/ event counter 50 output 8 reception unit transmission unit clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) output latch (p02) pm02 8 selector f xclk6 pom02 chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 234 (1) receive buffer register 6 (rxb6) this 8-bit register stores parallel data conv erted by receive shift register 6 (rxs6). each time 1 byte of data has been received, new receive data is transferred to this register from rxs6. if the data length is set to 7 bits, data is transferred as follows. ? in lsb-first reception, the receive data is transferred to bits 0 to 6 of rxb6 and the msb of rxb6 is always 0. ? in msb-first reception, the receive data is transferred to bits 1 to 7 of rxb6 and the lsb of rxb6 is always 0. if an overrun error (ove6) occurs, the rece ive data is not transferred to rxb6. rxb6 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset signal generation sets this register to ffh. (2) receive shift register 6 (rxs6) this register converts the serial data input to the r x d6 pin into parallel data. rxs6 cannot be directly manipulated by a program. (3) transmit buffer register 6 (txb6) this buffer register is used to set transmit data. tr ansmission is started when data is written to txb6. this register can be read or written by an 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. cautions 1. do not write data to txb6 when bi t 1 (txbf6) of asynchronous serial interface transmission status register 6 (asif6) is 1. 2. do not refresh (write the same value to) txb6 by software during a communication operation (when bits 7 and 6 (power6, txe6 ) of asynchronous serial interface operation mode register 6 (asim6) are 1 or when bits 7 and 5 (power6, rxe6) of asim6 are 1). 3. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. (4) transmit shift register 6 (txs6) this register transmits the data transferred from txb6 from the t x d6 pin as serial data. data is transferred from txb6 immediately after txb6 is written for the first tr ansmission, or immediately before intst6 occurs after one frame was transmitted for continuous transmission. da ta is transferred from txb6 and transmitted from the t x d6 pin at the falling edge of the base clock. txs6 cannot be directly manipulated by a program. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 235 10.3 registers controlling serial interface uart6 serial interface uart6 is controlle d by the following nine registers. ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? port mode register 0 (pm0) ? port register 0 (p0) ? port output mode register 0 (pom0) (1) asynchronous serial interface ope ration mode register 6 (asim6) this 8-bit register controls the serial comm unication operations of serial interface uart6. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. remark asim6 can be refreshed (the same value is wr itten) by software during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). figure 10-2. format of asynchronous serial inte rface operation mode register 6 (asim6) (1/2) address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 enables operation of t he internal operation clock txe6 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception notes 1. the output of the t x d6 pin goes high level and the input from the r x d6 pin is fixed to the high level when power6 = 0 during transmission. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), and receive buffer register 6 (rxb6) are reset. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 236 figure 10-2. format of asynchronous serial inte rface operation mode register 6 (asim6) (2/2) ps61 ps60 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl6 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enables/disables occurr ence of reception completion interrupt in case of error 0 ?intsre6? occurs in case of error (at this time, intsr6 does not occur). 1 ?intsr6? occurs in case of error (at this time, intsre6 does not occur). note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface reception error status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. to start the transmission, set power6 to 1 and then set txe6 to 1. to stop the transmission, clear txe6 to 0, and then clear power6 to 0. 2. to start the reception, set power6 to 1 and th en set rxe6 to 1. to stop the reception, clear rxe6 to 0, and then clear power6 to 0. 3. set power6 to 1 and then set rxe6 to 1 while a high level is input to the r x d6 pin. if power6 is set to 1 and rxe6 is set to 1 wh ile a low level is input, reception is started. 4. txe6 and rxe6 are synch ronized by the base clock (f xclk6 ) set by cksr6. to enable transmission or reception again, set txe6 or r xe6 to 1 at least two clocks of the base clock after txe6 or rxe6 has been cleared to 0. if txe6 or rxe6 is set within two clocks of the base clock, the transmission circuit or reception circui t may not be initialized. 5. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. 6. clear the txe6 and rxe6 bits to 0 be fore rewriting the ps61, ps60, and cl6 bits. 7. clear txe6 to 0 before re writing the sl6 bit. reception is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. 8. make sure that rxe6 = 0 when rewriting the isrm6 bit. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 237 (2) asynchronous serial interface recepti on error status register 6 (asis6) this register indicates an error status on completion of re ception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register is read-only by an 8-bit memory manipulation instruction. reset signal generation, or clearing bit 7 (power6) or bi t 5 (rxe6) of asim6 to 0 clears this register to 00h. 00h is read when this register is read. if a recept ion error occurs, read asis6 and then read receive buffer register 6 (rxb6) to clear the error flag. figure 10-3. format of asynchronous serial inte rface reception error status register 6 (asis6) address: ff53h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis6 0 0 0 0 0 pe6 fe6 ove6 pe6 status flag indicating parity error 0 if power6 = 0 or rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 or rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 or rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb6 register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface operati on mode register 6 (asim6). 2. for the stop bit of the recei ve data, only the first stop bit is checked regardless of the number of stop bits. 3. if an overrun error occurs , the next receive data is not wr itten to receive buffer register 6 (rxb6) but discarded. 4. if data is read from asis 6, a wait cycle is generated. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 238 (3) asynchronous serial interface tran smission status register 6 (asif6) this register indicates the status of transmission by se rial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register is read-only by an 8-bit memory manipulation instruction. reset signal generation, or clearing bit 7 (power6) or bi t 6 (txe6) of asim6 to 0 clears this register to 00h. figure 10-4. format of asynchronous serial in terface transmission status register 6 (asif6) address: ff55h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asif6 0 0 0 0 0 0 txbf6 txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is tr ansferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer regist er 6 (txb6) (if data transmi ssion is in progress) cautions 1. to transmit data conti nuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit data (second byte) to the txb6 register. if data is written to th e txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. 2. to initialize the transmission unit upon comple tion of continuous transmission, be sure to check that the txsf6 flag is ?0 ? after generation of the tran smission completion interrupt, and then execute initializat ion. if initiali zation is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. (4) clock selection register 6 (cksr6) this register selects the base cl ock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark cksr6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 239 figure 10-5. format of clock selection register 6 (cksr6) address: ff56h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 base clock (f xclk6 ) selection tps63 tps62 tps61 tps60 f prs = 2 mhz f prs = 4 mhz 0 0 0 0 f prs 2 mhz 4 mhz 0 0 0 1 f prs /2 1 mhz 2 mhz 0 0 1 0 f prs /2 2 500 khz 1 mhz 0 0 1 1 f prs /2 3 250 khz 500 khz 0 1 0 0 f prs /2 4 125 khz 250 khz 0 1 0 1 f prs /2 5 62.5 khz 125 khz 0 1 1 0 f prs /2 6 31.25 khz 62.5 khz 0 1 1 1 f prs /2 7 15.625 khz 31.25 khz 1 0 0 0 f prs /2 8 7.813 khz 15.625 khz 1 0 0 1 f prs /2 9 3.906 khz 7.813 khz 1 0 1 0 f prs /2 10 1.953 khz 3.906 khz 1 0 1 1 tm50 output note other than above setting prohibited note note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counter 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit timer/event counter 50 fi rst and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. caution make sure power6 = 0 wh en rewriting tps63 to tps60. remarks 1. f prs : peripheral hardware clock frequency 2. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 240 (5) baud rate generator c ontrol register 6 (brgc6) this register sets the division value of t he 8-bit counter of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. remark brgc6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). figure 10-6. format of baud rate ge nerator control register 6 (brgc6) address: ff57h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 0 0 0 0 0 0 setting prohibited 0 0 0 0 0 1 0 0 4 f xclk6 /4 0 0 0 0 0 1 0 1 5 f xclk6 /5 0 0 0 0 0 1 1 0 6 f xclk6 /6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 0 252 f xclk6 /252 1 1 1 1 1 1 0 1 253 f xclk6 /253 1 1 1 1 1 1 1 0 254 f xclk6 /254 1 1 1 1 1 1 1 1 255 f xclk6 /255 cautions 1. make sure that bit 6 (txe6) and bit 5 (rxe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. 2. the baud rate is the output clo ck of the 8-bit counter divided by 2. remarks 1. f xclk6 : frequency of base clock selected by the t ps63 to tps60 bits of cksr6 register 2. k: value set by mdl67 to mdl60 bits (k = 4, 5, 6, ..., 255) 3. : don?t care chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 241 (6) asynchronous serial interface control register 6 (asicl6) this register controls the serial communicati on operations of serial interface uart6. asicl6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 16h. caution asicl6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). figure 10-7. format of asynchronous serial interface control register 6 (asicl6) address: ff58h after reset: 16h r/w symbol 7 6 5 4 3 2 1 0 asicl6 0 0 0 0 0 0 dir6 txdlv6 dir6 first-bit specification 0 msb 1 lsb txdlv6 enables/disables inverting t x d6 output 0 normal output of t x d6 1 inverted output of t x d6 caution before rewriting the dir6 and txdlv6 bits, clear the txe6 a nd rxe6 bits to 0. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 242 (7) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p02/t x d6/ti000 pin for serial interface data output, clear pm02 to 0 and set the output latch of p02 to 1. when using the p03/r x d6/ti010/to00 pin for serial interface data inpu t, set pm03 to 1. the output latch of p03 at this time may be 0 or 1. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 10-8. format of port mode register 0 (pm0) address: ff20h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm0 pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0n p0n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) (8) port output mode resistors (pom0) this register set the output mode of port 0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to 00h. figure 10-9. format of pull-up resistor option register 7 pom07 symbol pom0 6 pom06 5 pom05 4 pom04 3 pom03 2 pom02 1 pom01 0 pom00 address ff38h after reset 00h r/w r/w pom0n p0n pin output mode selection (n = 0 to 7) 0 cmos output 1 n-ch open-drain output (p07:p-ch open-drain output) chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 243 10.4 operation of serial interface uart6 serial interface uart6 has the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 10.4.1 operation stop mode in this mode, serial communication cannot be executed; theref ore, the power consumption can be reduced. in addition, the pins can be used as ordinary po rt pins in this mode. to set the operation stop mode, clear bits 7, 6, and 5 (power6, txe6, and rxe6) of asim6 to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 6 (asim6). asim6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . txe6 enables/disables transmission 0 disables transmission o peration (synchronously resets the transmission circuit). rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to high level when power6 = 0 during transmission. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), and receive buffer register 6 (rxb6) are reset. caution clear power6 to 0 after clearing t xe6 and rxe6 to 0 to stop the operation. to start the communication, set power6 to 1, and then set txe6 or rxe6 to 1. remark to use the r x d6/p03/ti010/to00 and t x d6/p02/ti000 pins as general-purpose port pins, see chapter 4 port functions . chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 244 10.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? port mode register 0 (pm0) ? port register 0 (p0) ? port output mode register 0 (pom0) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the cksr6 register (see figure 10-5 ). <2> set the brgc6 register (see figure 10-6 ). <3> set bits 0 to 4 (isrm6, sl6, cl6, ps60, ps61) of the asim6 register (see figure 10-2 ). <4> set bits 0 and 1 (txdlv6, di r6) of the asicl6 register (see figure 10-7 ). <5> set bit 7 (power6) of the asim6 register to 1. <6> set bit 6 (txe6) of the asim6 register to 1. transmission is enabled. set bit 5 (rxe6) of the asim6 register to 1. reception is enabled. <7> write data to transmit buffer register 6 (txb6). data transmission is started. caution take the relationship with the other pa rty of communication when setting the port mode register and port register. the relationship between the register settings and pins is shown below. table 10-2. relationship between register settings and pins pin function power6 txe6 rxe6 pm02 p02 pm03 p03 uart6 operation t x d6/p02/ti000 r x d6/p03/ ti010/to00 0 0 0 note note note note stop p02/ti000 p03/ ti010/to00 0 1 note note 1 reception p02/ti000 r x d6 1 0 0 1 note note transmission t x d6 p03/ti010/to00 1 1 1 0 1 1 transmission/ reception t x d6 r x d6 note can be set as port function or 16-bit timer/event counter 00. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 245 remark : don?t care power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 pm0 : port mode register p0 : port output latch (2) communication operation (a) format and waveform example of normal transmit/receive data figures 10-10 and 10-11 show the format and waveform example of the normal transmit/receive data. figure 10-10. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (asim6). whether data is communicated with the lsb or msb first is specified by bit 1 (dir6) of asynchronous serial interface control register 6 (asicl6). whether the t x d6 pin outputs normal or inverted data is s pecified by bit 0 (txdlv6) of asicl6. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 246 figure 10-11. example of normal uart transmit/receive data waveform 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h, t x d6 pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: o dd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 247 (b) parity types and operation the parity bit is used to detect a bit error in communicati on data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive dat a, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parit y bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming t hat there is no parity bit when data is received. because there is no parity bit, a parity error does not occur. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 248 (c) normal transmission when bit 7 (power6) of asynchronous serial interface o peration mode register 6 (asim6) is set to 1 and bit 6 (txe6) of asim6 is then set to 1, transmission is enabl ed. transmission can be started by writing transmit data to transmit buffer register 6 (txb6 ). the start bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the data in txb6 is transferred to transmit sh ift register 6 (txs6). after that, the transmit data is sequentially output from txs6 to the t x d6 pin. when transmission is completed, the parity and stop bits set by asim6 are appended and a transmission completion interrupt request (intst6) is generated. transmission is stopped until the data to be transmitted next is written to txb6. figure 10-12 shows the timing of the transmission comp letion interrupt request (intst6). this interrupt occurs as soon as the last stop bit has been output. figure 10-12. normal transmission comp letion interrupt request timing 1. stop bit length: 1 intst6 d0 start d1 d2 d6 d7 stop t x d6 (output) parity 2. stop bit length: 2 t x d6 (output) intst6 d0 start d1 d2 d6 d7 parity stop chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 249 (d) continuous transmission the next transmit data can be written to transmit buffer re gister 6 (txb6) as soon as transmit shift register 6 (txs6) has started its shift operation. consequently, even while the intst6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. in addition, the txb6 register can be e fficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by readi ng bit 0 (txsf6) of asynchronous serial interface transmission status register 6 (asif6) when the transmission completion interrupt has occurred. to transmit data continuously, be sure to reference t he asif6 register to check the transmission status and whether the txb6 register can be written, and then write the data. caution the txbf6 and txsf6 flags of the asif6 regi ster change from ?10? to ?11?, and to ?01? during continuous transmission. to check the status, therefore, do not use a combination of the txbf6 and txsf6 flags for judgment. read only the txbf6 flag when executing continuous transmission. txbf6 writing to txb6 register 0 writing enabled 1 writing disabled caution to transmit data continuously, write the first transmit data (fi rst byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit da ta (second byte) to the txb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. the communication status can be checked using the txsf6 flag. txsf6 transmission status 0 transmission is completed. 1 transmission is in progress. cautions 1. to initialize the transm ission unit upon completion of continuous transmission, be sure to check that the txsf 6 flag is ?0? after generation of the transmission completion interrupt, and then execute initialization. if initialization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. 2. during continuous transmi ssion, the next transmission m ay complete before execution of intst6 interrupt servicing after tran smission of one data frame. as a countermeasure, detection can be performe d by developing a program that can count the number of transmit data and by referencing the txsf6 flag. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 250 figure 10-13 shows an example of the continuous transmission processing flow. figure 10-13. example of contin uous transmission processing flow write txb6. set registers. write txb6. transfer executed necessary number of times? yes read asif6 txbf6 = 0? no no yes transmission completion interrupt occurs? read asif6 txsf6 = 0? no no no yes yes yes yes completion of transmission processing transfer executed necessary number of times? remark txb6: transmit buffer register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 (transmit buffer data flag) txsf6: bit 0 of asif6 (trans mit shift register data flag) chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 251 figure 10-14 shows the timing of starting continuous transmission, and figure 10-15 shows the timing of ending continuous transmission. figure 10-14. timing of starting continuous transmission t x d6 start intst6 data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6 txs6 txbf6 txsf6 start start note note when asif6 is read, there is a period in which t xbf6 and txsf6 = 1, 1. therefore, judge whether writing is enabled using only the txbf6 bit. remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 252 figure 10-15. timing of ending continuous transmission t x d6 start intst6 data (n ? 1) data (n ? 1) data (n) data (n) data (n ? 1) ff parity stop stop data (n) parity stop txb6 txs6 txbf6 txsf6 power6 or txe6 start remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 power6: bit 7 of asynchronous serial interface operation mode register (asim6) txe6: bit 6 of asynchronous serial interface operation mode register (asim6) chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 253 (e) normal reception reception is enabled and the r x d6 pin input is sampled when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. the 8-bit counter of the baud rate generator st arts counting when the falling edge of the r x d6 pin input is detected. when the set value of baud rate generator control register 6 (brgc6) has been counted, the r x d6 pin input is sampled again ( in figure 10-16). if the r x d6 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, receptio n is started, and serial data is sequ entially stored in the receive shift register (rxs6) at the set baud rate. when the stop bi t has been received, the reception completion interrupt (intsr6) is generated and the data of rxs6 is written to receive buffer register 6 (rxb6). if an overrun error (ove6) occurs, however, the receiv e data is not written to rxb6. even if a parity error (pe6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and a recept ion error interrupt (intsr6/intsre 6) is generated on completion of reception. figure 10-16. reception completi on interrupt request timing r x d6 (input) intsr6 start d0 d1 d2 d3 d4 d5 d6 d7 parity rxb6 stop cautions 1. if a reception error occu rs, read asis6 and then rxb6 to clear the error flag. otherwise, an overrun error will occur when the next data is r eceived, and the reception error status will persist. 2. reception is always performed with the ?num ber of stop bits = 1? . the second stop bit is ignored. 3. be sure to read asynchro nous serial interface reception e rror status register 6 (asis6) before reading rxb6. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 254 (f) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 6 (asis6) is set as a result of data reception, a reception error interrupt r equest (intsr6/intsre6) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis6 in the reception error interrupt (intsr6/intsre6) servicing (see figure 10-3 ). the contents of asis6 are cleared to 0 when asis6 is read. table 10-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 6 (rxb6). the reception error interrupt can be separated into reception completion interrupt (intsr6) and error interrupt (intsre6) by clearing bit 0 (isrm6) of asynch ronous serial interface operation mode register 6 (asim6) to 0. figure 10-17. reception error interrupt 1. if isrm6 is cleared to 0 (recep tion completion interr upt (intsr6) and error interrupt (intsre6) are separated) (a) no error during recepti on (b) error during reception intsr6 intsre6 intsr6 intsre6 2. if isrm6 is set to 1 (error interrupt is included in intsr6) (a) no error during recepti on (b) error during reception intsre6 intsr6 intsre6 intsr6 chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 255 (g) noise filter of receive data the rxd6 signal is sampled with the base clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 10- 18, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 10-18. noise filter circuit internal signal b internal signal a match detector in base clock r x d6/p03/ ti010/to00 q in ld_en q 10.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart6. separate 8-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 3 to 0 (tps63 to tps60) of clock selectio n register 6 (cksr6) is supplied to each module when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is 1. this clock is called the base clock and its frequency is called f xclk6 . the base clock is fixed to low level when power6 = 0. ? transmission counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 6 (txe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when power6 = 1 and txe6 = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit buffer register 6 (txb6). if data are continuously transmitted, the counter is cleared to 0 agai n when one frame of data has been completely transmitted. if there is no data to be transmitted next, the count er is not cleared to 0 and continues counting until power6 or txe6 is cleared to 0. ? reception counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 5 (rxe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 256 figure 10-19. configuration of baud rate generator selector power6 8-bit counter match detector baud rate baud rate generator brgc6: mdl67 to mdl60 1/2 power6, txe6 (or rxe6) cksr6: tps63 to tps60 f prs f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 f prs /2 8 f prs /2 9 f prs /2 10 8-bit timer/ event counter 50 output f xclk6 remark power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 cksr6: clock selection register 6 brgc6: baud rate generator control register 6 (2) generation of serial clock a serial clock to be generated can be specified by usin g clock selection register 6 (cksr6) and baud rate generator control register 6 (brgc6). the clock to be input to the 8-bit counter can be set by bits 3 to 0 (tps63 to tps60) of cksr6 and the division value (f xclk6 /4 to f xclk6 /255) of the 8-bit counter can be set by bits 7 to 0 (mdl67 to mdl60) of brgc6. chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 257 10.4.4 calculation of baud rate (1) baud rate calculation expression the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk6 : frequency of base clock selected by tps63 to tps60 bits of cksr6 register k: value set by mdl67 to mdl60 bits of brgc6 register (k = 4, 5, 6, ..., 255) table 10-4. set value of tps63 to tps60 base clock (f xclk6 ) selection tps63 tps62 tps61 tps60 f prs = 2 mhz f prs = 4 mhz 0 0 0 0 f prs 2 mhz 4 mhz 0 0 0 1 f prs /2 1 mhz 2 mhz 0 0 1 0 f prs /2 2 500 khz 1 mhz 0 0 1 1 f prs /2 3 250 khz 500 khz 0 1 0 0 f prs /2 4 125 khz 250 khz 0 1 0 1 f prs /2 5 62.5 khz 125 khz 0 1 1 0 f prs /2 6 31.25 khz 62.5 khz 0 1 1 1 f prs /2 7 15.625 khz 31.25 khz 1 0 0 0 f prs /2 8 7.813 khz 15.625 khz 1 0 0 1 f prs /2 9 3.906 khz 7.813 khz 1 0 1 0 f prs /2 10 1.953 khz 3.906 khz 1 0 1 1 tm50 output note other than above setting prohibited note note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counte r 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. f xclk6 2 k chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 258 (2) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within th e permissible error range at the reception destination. 2. make sure that the baud rate error dur ing reception satisfies th e range shown in (4) permissible baud rate ra nge during reception. example: frequency of base clock = 4 mhz = 4,000,000 hz set value of mdl67 to mdl60 bits of brgc6 register = 00001101b (k = 13) target baud rate = 153600 bps baud rate = 4 m / (2 13) = 4000000 / (2 13) = 153846 [bps] error = (153846/153600 ? 1) 100 = 0.16 [%] (3) example of setting baud rate table 10-5. set data of baud rate generator f prs = 2.0 mhz f prs = 4.0 mhz baud rate [bps] tps63- tps60 k calculated value err [%] tps63- tps60 k calculated value err [%] 300 8h 13 301 0.16 8h 26 301 0.16 600 7h 13 601 0.16 7h 26 601 0.16 1200 6h 13 1202 0.16 6h 26 1202 0.16 2400 5h 13 2404 0.16 5h 26 2404 0.16 4800 4h 13 4808 0.16 4h 26 4808 0.16 9600 3h 13 9615 0.16 3h 26 9615 0.16 19200 2h 13 19231 0.16 2h 26 19231 0.16 24000 1h 21 23810 ? 0.79 1h 42 23810 ? 0.79 31250 1h 16 31250 0 1h 32 31250 0 38400 1h 13 38462 0.16 1h 26 38462 0.16 48000 0h 21 47619 ? 0.79 0h 42 47619 ? 0.79 76800 0h 13 76923 0.16 0h 26 76923 0.16 115200 0h 9 111111 ? 3.55 0h 17 117647 2.1 153600 ? ? ? ? 0h 13 153846 0.16 312500 ? ? ? ? 0h ? ? ? 625000 ? ? ? ? 0h ? ? ? remark tps63 to tps60: bits 3 to 0 of clock select ion register 6 (cksr6) (setting of base clock (f xclk6 )) k: value set by mdl67 to mdl60 bits of baud rate generator control register 6 (brgc6) (k = 4, 5, 6, ..., 255) f prs : peripheral hardware clock frequency err: baud rate error actual baud rate (baud rate with error) desired baud rate (correct baud rate) chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 259 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 10-20. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax data frame length of uart6 start bit bit 0 bit 1 bit 7 parity bit minimum permissible data frame length maximum permissible data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 10-20, the latch timing of the re ceive data is determined by t he counter set by baud rate generator control register 6 (brgc6) a fter the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart6 k: set value of brgc6 fl: 1-bit data length margin of latch timing: 2 clocks chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 260 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 10-6. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 4 +2.33% ? 2.44% 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the permissible error of reception depends on t he number of bits in one frame, input clock frequency, and division ratio (k). the higher t he input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc6 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2 k ? 2 2k 21k + 2 2k chapter 10 serial interface uart6 user?s manual u18685ej3v0ud 261 (5) data frame length during continuous transmission when data is continuously transmitted, th e data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. howeve r, the result of communica tion is not affected because the timing is initialized on the recepti on side when the start bit is detected. figure 10-21. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk6 , the following expression is satisfied. flstp = fl + 2/f xclk6 therefore, the data frame length during continuous transmission is: data frame length = 11 fl + 2/f xclk6 user?s manual u18685ej3v0ud 262 chapter 11 interrupt functions 11.1 interrupt function types the following two types of inte rrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrup ts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l). multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. if two or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed according to the priority of vectored in terrupt servicing. for the priority order, see table 11-1 . a standby release signal is generated a nd stop and halt modes are released. external interrupt requests and internal interrupt requests are provided as maskable interrupts. ? external: 8, internal: 10 (2) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control. 11.2 interrupt sources and configuration the pd179f11x, 179f12x microcontroller products have a tota l of 19 interrupt sources, including maskable interrupts and software interrupts. in addition, they also have up to four reset sources (see table 11-1 ). chapter 11 interrupt functions user?s manual u18685ej3v0ud 263 table 11-1. interrupt source list (1/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 0 intlvi low-voltage detection note 3 internal 0004h (a) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 pin input edge detection external 0010h (b) 7 intsre6 uart6 reception error generation 0012h 8 intsr6 end of uart6 reception 0014h 9 intst6 end of uart6 transmission 0016h 10 inttmh1 match between tmh1 and cmp01 (when compare register is specified) 001ah 11 inttmh0 match between tmh0 and cmp00 (when compare register is specified) 001ch 12 inttm50 match between tm50 and cr50 (when compare register is specified) 001eh 13 inttm000 match between tm00 and cr000 (when compare register is specified), ti010 pin valid edge detection (when capture register is specified) 0020h 14 inttm010 match between tm00 and cr010 (when compare register is specified), ti000 pin valid edge detection (when capture register is specified) 0022h 15 inttm51 note 4 match between tm51 and cr51 (when compare register is specified) internal 002ah (a) 16 intkr0 002ch maskable 17 intkr1 key interrupt detection external 002eh (c) software ? brk brk instruction execution ? 003eh (d) reset reset input poc power-on-clear lvi low-voltage detection note 5 reset ? wdt wdt overflow ? 0000h ? notes 1. the default priority determines t he sequence of processing vectored in terrupts if two or more maskable interrupts occur simultaneously. zero indicates the hi ghest priority and 17 indicates the lowest priority. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 11-1. 3. when bit 1 (lvimd) of the low-voltage det ection register (lvim) is cleared to 0. 4. when 8-bit timer/event counter 51 is used in the carri er generator mode, an interrupt is generated upon the timing when the inttm5h1 signal is generated (see figure 8-16 carrier generator mode operation timing ). 5. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 1. chapter 11 interrupt functions user?s manual u18685ej3v0ud 264 figure 11-1. basic configurati on of interrupt function (1/2) (a) internal maskable interrupt internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal (b) external maskable inte rrupt (intp0 to intp5) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag chapter 11 interrupt functions user?s manual u18685ej3v0ud 265 figure 11-1. basic configurati on of interrupt function (2/2) (c) external maskable interrupt (intkr) if mk ie pr isp internal bus interrupt request priority controller vector table address generator standby release signal key interrupt detector 1 when krmn = 1 (n = 0 to 14 note ) note krm9 to krm14 are available only in the 38-pin products. (d) software interrupt internal bus interrupt request priority controller vector table address generator if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag krm: key return mode register chapter 11 interrupt functions user?s manual u18685ej3v0ud 266 11.3 registers controlling interrupt functions the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag regi ster (if0l, if0h, if1l) ? interrupt mask flag register (mk0l, mk0h, mk1l) ? priority specification flag register (pr0l, pr0h, pr1l) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) ? program status word (psw) table 11-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. chapter 11 interrupt functions user?s manual u18685ej3v0ud 267 table 11-2. flags corresponding to interrupt request sources interrupt request flag interrupt mask flag priority specification flag interrupt source register register register intlvi lviif if0l lvimk mk0l lvipr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intsre6 sreif6 sremk6 srepr6 intsr6 srif6 if0h srmk6 mk0h srpr6 pr0h intst6 stif6 stmk6 stpr6 inttmh1 tmifh1 tmmkh1 tmprh1 inttmh0 tmifh0 tmmkh0 tmprh0 inttm50 tmif50 tmmk50 tmpr50 inttm000 tmif000 tmmk000 tmpr000 inttm010 tmif010 tmmk010 tmpr010 inttm51 note tmif51 if1l tmmk51 mk1l tmpr51 pr1l intkr0 krif0 krmk0 krpr0 intkr1 krif1 krmk1 krpr1 note when 8-bit timer/event counter 51 is used in the ca rrier generator mode, an inte rrupt is generated upon the timing when the inttm5h1 signal is generated (see figure 8-16 carrier generator mode operation timing ). chapter 11 interrupt functions user?s manual u18685ej3v0ud 268 (1) interrupt request flag re gisters (if0l, if0h, if1l) the interrupt request flags are set to 1 when the correspo nding interrupt request is g enerated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknow ledgment of an interrupt request or upon reset signal generation. when an interrupt is acknowledged, the interrupt req uest flag is automatically cleared and then the interrupt routine is entered. if0l, if0h, and if1l are set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h are combined to form 16-bit registers if0, they are set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to 00h. figure 11-2. format of interrupt request flag registers (if0l, if0h, if1l) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> 2 <1> <0> if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 0 stif6 srif6 address: ffe2h after reset: 00h r/w symbol 7 6 <5> <4> <3> 2 1 0 if1l 0 0 krif1 krif0 tmif51 0 0 0 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status cautions 1. be sure to clear bit 2 of if0h , and bits 0 to 2, 6, 7 of if1l to 0. 2. when operating a timer after standby release, operate it on ce after clearing the interrupt request flag. an interrupt requ est flag may be set by noise. 3. when manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (clr1). when descr ibing in c language, use a bit manipulation instruction such as ?if0l.0 = 0;? or ?_asm(?clr1 if0l, 0?);? because the co mpiled assembler must be a 1-bit memory manipulation instruction (clr1). if a program is described in c language usi ng an 8-bit memory manipulation instruction such as ?if0l &= 0xfe;? and compiled, it becom es the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if the request flag of another bit of the same interrupt request flag register (if0l) is set to 1 at the timing between ?mov a, if0l? and ?mov if 0l, a?, the flag is cleared to 0 at ?mov if0l, a?. therefore, care must be exercised when us ing an 8-bit memory manipulation instruction in c language. chapter 11 interrupt functions user?s manual u18685ej3v0ud 269 (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, and mk1l are set by a 1-bit or 8-bit memo ry manipulation instruction. when mk0l and mk0h are combined to form 16-bit registers mk0, they are set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 11-3. format of interrupt mask flag registers (mk0l, mk0h, mk1l) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> 2 <1> <0> mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 1 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol 7 6 <5> <4> <3> 2 1 0 mk1l 1 1 krmk1 krmk0 tmmk51 1 1 1 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled caution be sure to set bit 2 of mk0h, a nd bits 0 to 2, 6, 7 of mk1l to 1. chapter 11 interrupt functions user?s manual u18685ej3v0ud 270 (3) priority specification flag registers (pr0l, pr0h, pr1l) the priority specification flag regist ers are used to set the corresponding maskable interrupt priority order. pr0l, pr0h, and pr1l are set by a 1-bit or 8-bit memo ry manipulation instruction. if pr0l and pr0h are combined to form 16-bit registers pr0, they are set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 11-4. format of prio rity specification flag regi sters (pr0l, pr0h, pr1l) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> 2 <1> <0> pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 1 stpr6 srpr6 address: ffeah after reset: ffh r/w symbol 7 6 <5> <4> <3> 2 1 0 pr1l 1 1 krpr1 krpr0 tmpr51 1 1 1 xxprx priority level selection 0 high priority level 1 low priority level caution be sure to set bit 2 of pr0h, a nd bits 0 to 2, 6, 7 of pr1l to 1. chapter 11 interrupt functions user?s manual u18685ej3v0ud 271 (4) external interrupt rising edge en able register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp5. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to 00h. figure 11-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp 0 0 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn 0 0 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 5) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges caution be sure to clear bits 6 and 7 of egp and egn to 0. table 11-3 shows the ports corresponding to egpn and egnn. table 11-3. ports correspo nding to egpn and egnn detection enable register edge detection port interrupt request signal egp0 egn0 p120 intp0 egp1 egn1 p06 intp1 egp2 egn2 p05 intp2 egp3 egn3 p04 intp3 egp4 egn4 p27 intp4 egp5 egn5 reset/p123 intp5 caution select the port mode by clearing eg pn and egnn to 0 because an edge may be detected when the external interrupt func tion is switched to the port function. remark n = 0 to 5 chapter 11 interrupt functions user?s manual u18685ej3v0ud 272 (5) program status word (psw) the program status word is a register used to hold the instruction exec ution result and the current status for an interrupt request. the ie flag that sets maskable interr upt enable/disable and the isp fl ag that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out op erations using bit manipulation instructions and dedicated instructions (ei and di). when a vect ored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are aut omatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of t he acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with t he push psw instruction. they are restored from the stack with the reti, retb, and pop psw instructions. reset signal generation sets psw to 02h. figure 11-6. format of program status word <7> ie <6> z <5> rbs1 <4> ac <3> rbs0 2 0 <1> isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disabled) ie 0 1 disabled priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed enabled interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enabled) 0 1 chapter 11 interrupt functions user?s manual u18685ej3v0ud 273 11.4 interrupt servicing operations 11.4.1 maskable interrupt acknowledgment a maskable interrupt becomes acknowledgeable when the in terrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority in terrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt request until vectored interr upt servicing is performed are listed in table 18-4 below. for the interrupt request acknowledgment timing, see figures 11-8 and 11-9 . table 11-4. time from generation of maskable inte rrupt until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a di vide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledge d first. if two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is a cknowledged when it becomes acknowledgeable. figure 11-7 shows the interrupt request acknowledgment algorithm. if a maskable interrupt request is acknowledged, the content s are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the pr iority specification flag corresponding to the acknowledged interrupt are transferred to the isp flag. the vector table data deter mined for each interrupt request is the loaded into the pc and branched. restoring from an interrupt is possible by using the reti instruction. chapter 11 interrupt functions user?s manual u18685ej3v0ud 274 figure 11-7. interrupt request acknowledgment processing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any high-priority interrupt request among those simultaneously generated with pr = 0? if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledgment of mask able interrupt request (1 = enable, 0 = disable) isp: flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledg ed, or low-priority interrupt servicing) chapter 11 interrupt functions user?s manual u18685ej3v0ud 275 figure 11-8. interrupt request ac knowledgment timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 11-9. interrupt request ac knowledgment timing (maximum time) 33 clocks 32 clocks instruction divide instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) 11.4.2 software interrupt request acknowledgment a software interrupt request is acknowledged by brk instructi on execution. software interrupts cannot be disabled. if a software interrupt request is ackno wledged, the cont ents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and t he contents of the ve ctor table (003eh, 003fh) are loaded into the pc and branched. restoring from a software interrupt is possi ble by using the retb instruction. caution do not use the reti instruction fo r restoring from the software interrupt. chapter 11 interrupt functions user?s manual u18685ej3v0ud 276 11.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt re quest is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the inte rrupt request acknowledgment enabled state is selected (ie = 1). when an interrupt request is acknowledged, inte rrupt request acknowledgment becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgment. moreover, even if interrupts are enabled, multiple interr upt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an in terrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for mu ltiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. inte rrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower prio rity are held pending. when servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. table 11-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 11-10 shows multiple interrupt servicing examples. table 11-5. relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request pr = 0 pr = 1 multiple interrupt request interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 software interrupt request isp = 0 { { maskable interrupt isp = 1 { { { software interrupt { { { remarks 1. : multiple interrupt servicing enabled 2. : multiple interrupt servicing disabled 3. isp and ie are flags contained in the psw. isp = 0: an interrupt with higher priority is being serviced. isp = 1: no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0: interrupt request acknowledgment is disabled. ie = 1: interrupt request acknowledgment is enabled. 4. pr is a flag contained in pr0l, pr0h, and pr1l. pr = 0: higher priority level pr = 1: lower priority level chapter 11 interrupt functions user?s manual u18685ej3v0ud 277 figure 11-10. examples of multip le interrupt se rvicing (1/2) example 1. multiple inte rrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0 ie = 1 ie = 1 ie = 1 during servicing of interrupt intxx, two interrupt re quests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt re quest is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti ie = 1 ie = 1 interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and mu ltiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgment disabled chapter 11 interrupt functions user?s manual u18685ej3v0ud 278 figure 11-10. examples of multip le interrupt se rvicing (2/2) example 3. multiple interrupt servicing do es not occur because inte rrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0 ie = 1 ie = 1 interrupts are not enabled during servicing of interrupt int xx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt serv icing does not take place. the intyy interrupt request is held pending, and is acknowledged following ex ecution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgment disabled chapter 11 interrupt functions user?s manual u18685ej3v0ud 279 11.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the ne xt instruction. these instructions (interrupt request hol d instructions) are listed below. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw. bit, cy ? mov1 cy, psw. bit ? and1 cy, psw. bit ? or1 cy, psw. bit ? xor1 cy, psw. bit ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? push psw ? pop psw ? bt psw. bit, $addr16 ? bf psw. bit, $addr16 ? btclr psw. bit, $addr16 ? ei ? di ? manipulation instructions for the if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, and pr1l registers. caution the brk instruction is not one of the above-listed interrupt re quest hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared. therefore, even if a maskable interrupt re quest is generated during execution of the brk instruction, the interrupt re quest is not acknowledged. figure 11-11 shows the timing at which interrupt requests are held pending. figure 11-11. interrupt request hold instruction n instruction m psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other t han interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request). user?s manual u18685ej3v0ud 280 chapter 12 key interrupt function 12.1 functions of key interrupt a key interrupt (intkr0 and intkr1) can be generated by setting the key return mode register 0, 1 (krml and krmh) and inputting a falling edge to the key interrupt input pins note . when using the reset/p123/intp5/kr8 pin for kr8, set bi t 3 (rstm) of the reset pin mode register (rstmask) to "1". note 30-pin products: kr0 to kr8 38-pin products: kr0 to kr14 table 12-1. assignment of k ey interrupt detection pins flag description krmlm controls krm signal in 1-bit units. krmhm controls krn signal in 1-bit units. remark m = 0 to 7, n = 8 to 14 12.2 configuration of key interrupt the key interrupt includes the following hardware. table 12-2. configuration of key interrupt item configuration control register key return mode register 0 (krml) key return mode register 1 (krmh) figure 12-1. block diagra m of key interrupt (1/2) (a) key interrupt (intkr0) key return mode register 0 (krml) intkr0 kr0 krm7 krm6 krm1 krm0 kr1 kr6 kr7 chapter 12 key interrupt function user?s manual u18685ej3v0ud 281 figure 12-1. block diagra m of key interrupt (2/2) (b) key interrupt (intkr1) key return mode register 1 (krmh) intkr1 kr8 krm14 krm13 krm9 krm8 kr9 note1 kr13 note1 kr14 note1 note2 note2 note2 notes 1. 38-pin products only 2. these bits are fixed to ?0? in the 30-pin products. 12.3 register controlling key interrupt (1) key return mode register 0 (krml) this register controls the krm0 to krm7 bits using the kr0 to kr7 signals, respectively. krml is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets krml to 00h. figure 12-2. format of key retu rn mode register 0 (krml) address: ff6eh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 krml krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 pe6 status flag indicating parity error 0 does not detect key interrupt signal 1 detects key interrupt signal cautions 1. if any of the krm0 to krm 7 bits used is set to 1, set bits 0 to 7 of the corresponding pull-up resistor register 1 (pu1) to 1. 2. if krml is changed, the interrupt request fl ag may be set. therefo re, disable interrupts and then change the krml register. clear the in terrupt request flag and enable interrupts. 3. the bits not used in the key inte rrupt mode can be used as normal ports. chapter 12 key interrupt function user?s manual u18685ej3v0ud 282 (2) key return mode register 1 (krmh) this register controls the krm8, and krm9 to krm14 note bits using the kr8, and kr9 to kr14 note signals, respectively. krmh is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets krmh to 00h. figure 12-3. format of key retu rn mode register 1 (krmh) address: ff6fh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 krmh 0 krm14 note krm13 note krm12 note krm11 note krm10 note krm9 note krm8 pe6 status flag indicating parity error 0 does not detect key interrupt signal 1 detects key interrupt signal note 38-pin products only cautions 1. if any of the krm8 to krm14 bits used is set to 1, set bi ts 0 to 5 of the corresponding pull- up resistor register 3 (pu3) to 1, and bit 3 of the corresponding pull-up resistor register 12 (pu12) to 1. 2. if krmh is changed, the interrupt request fl ag may be set. therefo re, disable interrupts and then change the krmh register. clear the in terrupt request flag and enable interrupts. 3. the bits not used in the key inte rrupt mode can be used as normal ports. 4. for the 30-pin products, be sure to set bits 0 to 6 of krmh and pm3 to ?0?. user?s manual u18685ej3v0ud 283 chapter 13 standby function 13.1 standby function and configuration 13.1.1 standby function the standby function is designed to reduce the operating current of the system. the following two modes are available. (1) halt mode halt instruction execution se ts the halt mode. in the halt mode, the cpu operation clock is stopped. if the high-speed system clock oscillator, internal high-speed osc illator, or internal low-sp eed oscillator is operating before the halt mode is set, oscillation of each clock c ontinues. in this mode, the operating current is not decreased as much as in the stop m ode, but the halt mode is effective fo r restarting operation immediately upon interrupt request generation and carry ing out intermittent operations frequently. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the high-speed system clock oscillator and internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the cpu operating current. because this mode can be cleared by an interrupt reques t, it enables intermittent operations to be carried out. however, because a wait time is required to secure th e oscillation stabilization time after the stop mode is released when the x1 clock is selected, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. in either of these two modes, all the contents of registers, flags and data me mory just before the standby mode is set are held. the i/o port output latches an d output buffer statuses are also held. caution when shifting to the stop mode, be sure to stop the peripheral ha rdware operation operating with main system clock before executing stop instruction. 13.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) remark for the registers that start, st op, or select the clock, see chapter 5 clock generator . chapter 13 standby function user?s manual u18685ej3v0ud 284 (1) oscillation stabilization time c ounter status register (ostc) this is the register that indicates t he count status of the x1 clock oscillati on stabilization time counter. when x1 clock oscillation starts with the internal high-speed os cillation clock used as the cpu clock, the x1 clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lvi, and wdt), the stop instruction and mstop (bit 7 of moc register) = 1 clear ostc to 00h. figure 13-1. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status f x = 1 mhz f x = 2 mhz f x = 4 mhz 0 0 0 0 0 less than 2 11 /f x less than 2.04 ms less than 1.02 ms less than 510 s 1 0 0 0 0 2 11 /f x min. 2.04 ms min 1.02 ms min 510 s min 1 1 0 0 0 2 13 /f x min. 8.20 ms min 4.10 ms min 2.04 ms min 1 1 1 0 0 2 14 /f x min. 16.38 ms min. 8.19 ms min. 4.10 ms min 1 1 1 1 0 2 15 /f x min. 32.77 ms min. 16.38 ms min. 8.19 ms min. 1 1 1 1 1 2 16 /f x min. 65.45 ms min. 32.77 ms min. 16.38 ms min. cautions 1. after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. 2. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 3. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 13 standby function user?s manual u18685ej3v0ud 285 (2) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the operation waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confirm with ostc that the desired oscillation stabilization time has elaps ed after the stop mode is released. the oscillation stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 05h. figure 13-2. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection f x = 1 mhz f x = 2 mhz f x = 4 mhz 0 0 1 2 11 /f x 2.04 ms 1.02 ms 510 s 0 1 0 2 13 /f x 8.19 ms 4.10 ms 2.04 ms 0 1 1 2 14 /f x 16.38 ms 8.19 ms 4.10 ms 1 0 0 2 15 /f x 32.77 ms 16.38 ms 8.19 ms 1 0 1 2 16 /f x 65.45 ms 32.77 ms 16.38 ms other than above setting prohibited cautions 1. to set the stop mode when the x1 clock is used as the cpu clock, set osts before executing the stop instruction. 2. do not change the value of the osts register during the x1 clock oscillation stabilization time. 3. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 4. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 13 standby function user?s manual u18685ej3v0ud 286 13.2 standby function operation 13.2.1 halt mode (1) halt mode the halt mode is set by executing t he halt instruction. halt mode can be set regardless of whether the cpu clock before the setting was the high-speed system clo ck, or internal high-speed oscillation clock. the operating statuses in t he halt mode are shown below. table 13-1. operating statuses in halt mode when halt instruction is executed while cpu is operating on main system clock halt mode setting item when cpu is operating on internal high-speed oscillation clock (f rh ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f exclk ) system clock clock supply to the cpu is stopped f rh operation continues (cannot be stopped) status before halt mode was set is continued f x status before halt mode was set is continued operation continues (cannot be stopped) status before halt mode was set is retained main system clock f exclk operates or stops by external cl ock input operation continues (cannot be stopped) f rl status before halt mode was set is continued cpu flash memory operation stopped ram port (latch) status before halt mode was set is retained 16-bit timer/event counter 00 50 8-bit timer/event counter 51 h0 8-bit timer h1 operable watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. serial interface uart6 power-on-clear function low-voltage detection function external interrupt operable remark f rh : internal high-speed oscillation clock f x : x1 clock f exclk : external main system clock f rl : internal low-speed oscillation clock chapter 13 standby function user?s manual u18685ej3v0ud 287 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 13-3. halt mode release by interrupt request generation halt instruction wait note normal operation halt mode normal operation oscillation high-speed system clock, internal high-speed oscillation clock status of cpu standby release signal interrupt request note the wait time is as follows: when vectored interrupt servicing is carried out: 8 or 9 clocks when vectored interrupt servicing is not carried out: 2 or 3 clocks remark the broken line indicates the case when the interrupt request which has released the standby mode is acknowledged. (b) release by reset signal generation when the reset signal is generated, halt mode is re leased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 13-4. halt mode release by reset (1/2) (1) when high-speed system clock is used as cpu clock halt instruction reset signal high-speed system clock (x1 oscillation) halt mode reset period oscillates oscillation stopped oscillates status of cpu normal operation (high-speed system clock) oscillation stabilization time (2 11 /f x to 2 16 /f x ) normal operation (internal high-speed oscillation clock) oscillation stopped starting x1 oscillation is specified by software. reset processing (60 to 160 s) remark f x : x1 clock oscillation frequency chapter 13 standby function user?s manual u18685ej3v0ud 288 figure 13-4. halt mode release by reset (2/2) (2) when internal high-speed osc illation clock is used as cpu clock halt instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) halt mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu wait for oscillation accuracy stabilization (0.48 to 1.44ms) reset processing (60 to 160 s) remark f x : x1 clock oscillation frequency table 13-2. operation in response to interrupt request in halt mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 halt mode held reset ? ? reset processing : don?t care 13.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing t he stop instruction, and it can be se t only when the cpu clock before the setting was the main system clock. caution because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilizat ion time select register (osts) has elapsed. the operating statuses in t he stop mode are shown below. chapter 13 standby function user?s manual u18685ej3v0ud 289 table 13-3. operating statuses in stop mode when stop instruction is executed while cpu is operating on main system clock stop mode setting item when cpu is operating on internal high-speed oscillation clock (f rh ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f exclk ) system clock clock supply to the cpu is stopped f rh f x stopped main system clock f exclk input invalid f rl status before stop mode was set is continued cpu flash memory operation stopped ram port (latch) status before stop mode was set is retained 16-bit timer/event counter 00 note 1 operation stopped 50 note 1 operable only when ti50 is se lected as the count clock 8-bit timer/event counter 51 note 1 operable only when ti51 is selected, or tmh1 ca rrier clock is selected as the count clock when 8-bit timer h1 operates in carrier generator mode h0 operable only when tm50 output is selected as the count clock during 8- bit timer/event counter 50 operation 8-bit timer h1 operable only when f rl or f rl /2 7 is selected as the count clock watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. serial interface uart6 operable only when tm50 output is selected as the serial clock during 8-bit timer/event counter 50 operation power-on-clear function low-voltage detection function external interrupt operable note do not start operation of t hese functions on the external clock input from peripheral hardware pins in the stop mode. remark f rh : internal high-speed oscillation clock f x : x1 clock f exclk : external main system clock f rl : internal low-speed oscillation clock cautions 1. to use the peripheral ha rdware that stops operation in the stop mode, and the peripheral hardware for which the clock that stops oscillati ng in the stop mode after the stop mode is released, restart the peripheral hardware. 2. even if ?internal low-speed oscillator can be stopped by software? is selected by the option byte, the internal low-speed osc illation clock continues in the stop mode in the status before the stop mode is set. to stop the internal low- speed oscillator?s oscillation in the stop mode, stop it by software and then execute the stop instruction. 3. to shorten oscillation stabiliz ation time after the stop mode is released when the cpu operates with the high-speed system clock (x1 oscillation) , temporarily switch the cpu clock to the internal high-speed oscillation cl ock before the next execution of the stop instruction. before changing the cpu clock from the internal high-speed oscillation clock to the hi gh-speed system chapter 13 standby function user?s manual u18685ej3v0ud 290 clock (x1 oscillation) after the stop mode is released, check the oscilla tion stabilization time with the oscillation stabilization time counter status register (ostc). cautions 4. be sure to confirm that the operation of the high-speed internal osc illator is stable (rsts = 1) when performing a stop instruction. (2) stop mode release figure 13-5. operation timing when stop m ode is released (when unmasked interrupt request is generated) stop mode stop mode release high-speed system clock (x1 oscillation) high-speed system clock (external clock input) internal high-speed oscillation clock high-speed system clock (x1 oscillation) is selected as cpu clock when stop instruction is executed high-speed system clock (external clock input) is selected as cpu clock when stop instruction is executed internal high-speed oscillation clock is selected as cpu clock when stop instruction is executed wait for oscillation accuracy stabilization (0.48 to 1.441 ms) halt status (oscillation stabilization time set by osts) clock switched automatically clock switched by software high-speed system clock high-speed system clock wait note wait note high-speed system clock internal high-speed oscillation clock note the wait time is as follows: when vectored interrupt servicing is carried out: 8 or 9 clocks when vectored interrupt servicing is not carried out: 2 or 3 clocks the stop mode can be released by the following two sources. chapter 13 standby function user?s manual u18685ej3v0ud 291 (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the st op mode is released. if interrupt acknowledgment is enabled, vectored interrupt servicing is carried ou t. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 13-6. stop mode release by interrupt request generation (1/2) (1) when high-speed system clock (x 1 oscillation) is used as cpu clock normal operation (high-speed system clock) normal operation (high-speed system clock) oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait (halt mode status) oscillation stopped high-speed system clock (x1 oscillation) status of cpu oscillation stabilization time (set by osts) interrupt request (2) when high-speed system clock (external clock in put) is used as cpu clock interrupt request stop instruction standby release signal status of cpu high-speed system clock (external clock input) normal operation (high-speed system clock) oscillates stop mode oscillation stopped wait note normal operation (high-speed system clock) oscillates note the wait time is as follows: when vectored interrupt servicing is carried out: 8 or 9 clocks when vectored interrupt servicing is not carried out: 2 or 3 clocks remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged. chapter 13 standby function user?s manual u18685ej3v0ud 292 figure 13-6. stop mode release by interrupt request generation (2/2) (3) when internal high-speed osc illation clock is used as cpu clock wait note wait for oscillation accuracy stabilization (0.48 to 1.44 ms) oscillates normal operation (internal high-speed oscillation clock) stop mode oscillation stopped oscillates normal operation (internal high-speed oscillation clock) internal high-speed oscillation clock status of cpu standby release signal stop instruction interrupt request note the wait time is as follows: when vectored interrupt servicing is carried out: 8 or 9 clocks when vectored interrupt servicing is not carried out: 2 or 3 clocks remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged. chapter 13 standby function user?s manual u18685ej3v0ud 293 (b) release by reset signal generation when the reset signal is generated, stop mode is released, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 13-7. stop mode release by reset (1) when high-speed system clock is used as cpu clock stop instruction reset signal high-speed system clock (x1 oscillation) normal operation (high-speed system clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stabilization time (2 11 /f x to 2 16 /f x ) oscillation stopped starting x1 oscillation is specified by software. oscillation stopped reset processing (60 to 160 s) (2) when internal high-speed osc illation clock is used as cpu clock stop instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped status of cpu oscillates oscillation stopped wait for oscillation accuracy stabilization (0.48 to 1.44 ms) reset processing (60 to 160 s) remark f x : x1 clock oscillation frequency table 13-4. operation in response to interrupt request in stop mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 stop mode held reset ? ? reset processing : don?t care user?s manual u18685ej3v0ud 294 chapter 14 reset function the following four operations are av ailable to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (4) internal reset by comparison of supply voltage and detection voltage of low- power-supply detector (lvi) external and internal resets have no functional differences. in both cases, program exec ution starts at the address at 0000h and 0001h when the reset signal is generated. a reset is applied when a low level is input to the reset pin, the watchdog timer overflows, or by poc and lvi circuit voltage detection, and each item of hardware is set to the status s hown in tables 14-1 and 14-2. each pin is high impedance during reset signal generation or during the osc illation stabilization time just after a reset release. when a low level is input to the reset pin, the device is reset. it is rel eased from the reset status when a high level is input to the reset pin and pr ogram execution is start ed with the internal high-speed oscillation clock after reset processing. a reset by the watchdog timer is automat ically released, and program execution starts using the internal high-speed oscillation clock (see figures 14-2 to 14-4 ) after reset processing. reset by poc and lvi circuit power supply detection is aut omatically released when v dd v poc or v dd v lvi after the reset, and program execution starts using the internal high-speed oscillation clock (see chapter 15 power-on-clear circuit and chapter 16 low-voltage detector ) after reset processing. cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, the x1 clock, internal high- speed oscillation clock, and internal low- speed oscillation clock stop oscillating. extern al main system clock input become invalid. 3. when the stop mode is released by a reset , the stop mode contents are held during reset input. however, the port pins become high-impedance. chapter 14 reset function user?s manual u18685ej3v0ud 295 figure 14-1. block diagram of reset function lvirf wdtrf reset control flag register (resf) internal bus watchdog timer reset signal reset power-on-clear circuit reset signal low-voltage detector reset signal reset signal reset signal to lvim/lvis register clear set clear set caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level selection register chapter 14 reset function user?s manual u18685ej3v0ud 296 figure 14-2. timing of reset by reset input delay delay (5 s (typ.)) hi-z normal operation cpu clock reset period (oscillation stop) normal operation (internal high-speed oscillation clock) reset internal reset signal port pin high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. reset processing (60 to 160 s) wait for oscillation accuracy stabilization (0.48 to 1.44 ms) figure 14-3. timing of reset due to watchdog timer overflow normal operation reset period (oscillation stop) cpu clock watchdog timer overflow internal reset signal hi-z port pin high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) reset processing (60 to 160 s) wait for oscillation accuracy stabilization (0.48 to 1.44 ms) caution a watchdog timer internal reset resets the watchdog timer. chapter 14 reset function user?s manual u18685ej3v0ud 297 figure 14-4. timing of reset in stop mode by reset input delay normal operation cpu clock reset period (oscillation stop) reset internal reset signal stop instruction execution stop status (oscillation stop) high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock hi-z port pin starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) reset processing (60 to 160 s) delay (5 s (typ.)) wait for oscillation accuracy stabilization (0.48 to 1.44 ms) remark for the reset timing of the power-on-cl ear circuit and low-voltage detector, see chapter 15 power- on-clear circuit and chapter 16 low-voltage detector . table 14-1. operation statuses during reset period item during reset period system clock clock suppl y to the cpu is stopped. f rh operation stopped f x operation stopped (pin is i/o port mode) main system clock f exclk clock input invalid (pin is i/o port mode) f rl cpu flash memory ram port (latch) 16-bit timer/event counter 00 50 8-bit timer/event counter 51 h0 8-bit timer h1 watchdog timer serial interface uart6 operation stopped power-on-clear function operable low-voltage detection function external interrupt operation stopped remark f rh : internal high-speed oscillation clock f x : x1 oscillation clock f exclk : external main system clock f rl : internal low-speed oscillation clock chapter 14 reset function user?s manual u18685ej3v0ud 298 table 14-2. hardware statuses after reset acknowledgment (1/2) hardware after reset acknowledgment note 1 program counter (pc) the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 port registers (p0 to p2, p3 note 3 , p12) (output latches) 00h port mode registers (pm0 to pm2, pm3 note 3 , pm12) ffh pull-up resistor option registers (pu0 to pu2, pu3 note 3 , pu12) 00h port output mode resistors (pom0 to pom2, pom3 note 3 , pom12) 00h pull-up resistor option registers (pu0 to pu2, pu3 note 3 , pu12) 00h (08h for pu12) flmd0 pull-up/pull-down control register (fpctl) 00h flmd0 pull-up/pull-down enable register (fpen) 00h internal memory size swit ching register (ims) cfh note 4 clock operation mode select register (oscctl) 00h processor clock control register (pcc) 01h internal oscillation mode register (rcm) 80h main osc control register (moc) 80h main clock mode register (mcm) 00h oscillation stabilization time counter status register (ostc) 00h oscillation stabilization time select register (osts) 05h timer counter 00 (tm00) 0000h capture/compare registers 000, 010 (cr000, cr010) 0000h mode control register 00 (tmc00) 00h prescaler mode register 00 (prm00) 00h capture/compare control register 00 (crc00) 00h 16-bit timer/event counter 00 timer output control register 00 (toc00) 00h notes 1. during reset signal generation or oscillation stabiliz ation time wait, only the pc contents among the hardware statuses becom e undefined. all other hardware st atuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. 38-pin products only. 4. the initial value of the internal memo ry size switching register after a re set release is fixed (ims = cfh) in all the pd179f11x, 179f12x microcontroller products, regardless of the in ternal memory capacity. therefore, after a reset is released, be sure to set the following values for each product. flash memory version ( pd179f11x, 179f12x microcontrollers) ims pd179f110 41h pd179f111 42h pd179f112, 179f122 04h pd179f113, 179f123 c6h pd179f114, 179f124 c8h chapter 14 reset function user?s manual u18685ej3v0ud 299 table 14-2. hardware statuses after reset acknowledgment (2/2) hardware status after reset acknowledgment note 1 timer counters 50, 51 (tm50, tm51) 00h compare registers 50, 51 (cr50, cr51) 00h timer clock selecti on registers 50, 51 (tcl50, tcl51) 00h 8-bit timer/event counters 50, 51 mode control registers 50, 51 (tmc50, tmc51) 00h compare registers 00, 10, 01, 11 (cmp00, cmp10, cmp01, cmp11) 00h mode registers (tmhmd0, tmhmd1) 00h 8-bit timers h0, h1 carrier control register 1 (tmcyc1) note 2 00h watchdog timer enable register (wdte) 1ah/9ah note 3 receive buffer register 6 (rxb6) ffh transmit buffer register 6 (txb6) ffh asynchronous serial interface operat ion mode register 6 (asim6) 01h asynchronous serial interface reception error status register 6 (asis6) 00h asynchronous serial interface transmi ssion status register 6 (asif6) 00h clock selection register 6 (cksr6) 00h baud rate generator control register 6 (brgc6) ffh asynchronous serial interface c ontrol register 6 (asicl6) 16h serial interface uart6 input switch control register (isc) 00h key interrupt key return mode register 0, 1 (krml, krmh) 00h reset control flag register (resf) 00h note 4 reset function reset pin mode register (rstmask) 00h low-voltage detection register (lvim) 00h note 4 low-voltage detection level selection register (lvis) 00h note 4 low-voltage detector ram data retention control register (lvdet) undefined request flag registers 0l, 0h, 1l (if0l, if0h, if1l) 00h mask flag registers 0l, 0h, 1l (mk0l, mk0h, mk1l) ffh priority specification flag registers 0l, 0h, 1l (pr0l, pr0h, pr1l) ffh external interrupt rising edge enable register (egp) 00h interrupt external interrupt falling edge enable register (egn) 00h notes 1. during reset signal generation or oscillation stabiliz ation time wait, only the pc contents among the hardware statuses becom e undefined. all other hardware st atuses remain unchanged after reset. 2. 8-bit timer h1 only. 3. the reset value of wdte is determined by the option byte setting. 4. these values vary depending on the reset source. reset source register reset input reset by poc reset by wdt reset by lvi wdtrf bit set (1) held resf lvirf bit cleared (0) cleared (0) held set (1) lvim lvis cleared (00h) cleared (00h) cleared (00h) held chapter 14 reset function user?s manual u18685ej3v0ud 300 14.1 register for confirming reset source many internal reset generation sources exist in the pd179f11x, 179f12x microcontrollers . the reset control flag register (resf) is used to store whic h source has generated the reset request. resf can be read by an 8-bit memo ry manipulation instruction. reset input, reset by power-on-clear (poc) circuit, and reading resf set resf to 00h. figure 14-5. format of reset control flag register (resf) address: ffach after reset: 00h note r symbol 7 6 5 4 3 2 1 0 resf 0 0 0 wdtrf 0 0 0 lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data by a 1-bi t memory manipulation instruction. the status of resf when a reset reques t is generated is shown in table 14-3. table 14-3. resf status when reset request is generated reset source flag reset input reset by poc reset by wdt reset by lvi wdtrf set (1) held lvirf cleared (0) cleared (0) held set (1) user?s manual u18685ej3v0ud 301 chapter 15 power-on-clear circuit 15.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? generates internal reset signal at power on. the reset signal is released when the supply voltage (v dd ) exceeds 1.8 v 0.1 v. ? compares supply voltage (v dd ) and detection voltage (v poc = 1.8 v 0.1 v), generates internal reset signal when v dd < v poc . caution if an internal reset signal is generated in the poc circuit, th e reset control flag register (resf) is cleared to 00h. remark the pd179f11x, 179f12x microcontrollers incorporate mu ltiple hardware functions that generate an internal reset signal. a fl ag that indicates the reset source is lo cated in the reset control flag register (resf) for when an internal reset signal is gener ated by the watchdog timer (wdt) or low-voltage- detector (lvi). resf is not cleared to 00h and the flag is set to 1 when an internal reset signal is generated by wdt or lvi. for details of resf, see chapter 14 reset function . chapter 15 power-on-clear circuit user?s manual u18685ej3v0ud 302 15.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 15-1. figure 15-1. block diagram of power-on-clear circuit ? + reference voltage source internal reset signal v dd v dd 15.3 operation of power-on-clear circuit ? an internal reset signal is generated on power application. when the supply voltage (v dd ) exceeds the detection voltage (v poc = 1.8 v 0.1 v), the reset status is released. ? the supply voltage (v dd ) and detection voltage (v poc = 1.8 v 0.1 v) are compared. when v dd < v poc , the internal reset signal is generated. it is released when v dd v poc . the timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown below. chapter 15 power-on-clear circuit user?s manual u18685ej3v0ud 303 figure 15-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector note 4 note 1 internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) (when x1 oscillation is selected) starting oscillation is specified by software. v lvi operation stops wait for voltage stabilization (1.96 to 5.4 ms) normal operation (internal high-speed oscillation clock) note 2 operation stops reset period (oscillation stop) reset period (oscillation stop) wait for oscillation accuracy stabilization (0.48 to 1.44 ms) normal operation (internal high-speed oscillation clock) note 2 starting oscillation is specified by software. starting oscillation is specified by software. cpu 0 v supply voltage (v dd ) 1.8 v wait for voltage stabilization (1.96 to 5.4 ms) normal operation (internal high-speed oscillation clock ) note 2 set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt internal reset signal reset processing (60 to 160 s) reset processing (60 to 160 s) reset processing (60 to 160 s) notes 1. the oscillation accuracy stabilizati on time of the internal high-speed oscillation clock is included in the internal voltage stabilization time. 2. the cpu clock can be switched from the internal high-speed oscillat ion clock to the high-speed system clock. to use the x1 clock, use the ostc register to confirm the lapse of the oscillation stabilization time. caution set the low-voltage detector by software after the reset status is released (see chapter 16 low-voltage detector). remark v lvi : lvi detection voltage v poc : poc detection voltage chapter 15 power-on-clear circuit user?s manual u18685ej3v0ud 304 15.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the oper ation of the microcontroller can be arbitrarily set by taking the following action. chapter 15 power-on-clear circuit user?s manual u18685ej3v0ud 305 figure 15-3. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector no wdtrf of resf register = 1? lvirf of resf register = 1? yes user?s manual u18685ej3v0ud 306 chapter 16 low-voltage detector 16.1 functions of low-voltage detector the low-voltage detector (lvi) has the following functions. ? the lvi circuit compares the supply voltage (v dd ) with the detection voltage (v lvi ) or the input voltage from an external input pin (exlvi ) with the detection voltage (v exlvi = 1.21 v (typ.): fixed) , and generates an internal reset or internal interrupt signal. ? the supply voltage (v dd ) or input voltage from an external input pin (exlvi) can be selected by software. ? reset or interrupt function can be selected by software. ? detection levels (11 levels) of supply voltage can be changed by software. ? operable in stop mode. ? ram data retention detection (refer 16.6 ram data retention detector ) the reset and interrupt signals are generated as follows depending on selection by software. selection of level detection of supply voltage (v dd ) (lvisel = 0) selection level detection of input voltage from external input pin (exlvi) (lvisel = 1) selects reset (lvimd = 1). selects interrupt (lvimd = 0). selects reset (lvimd = 1). selects interrupt (lvimd = 0). generates an internal reset signal when v dd < v lvi and releases the reset signal when v dd v lvi . generates an internal interrupt signal when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). generates an internal reset signal when exlvi < v exlvi and releases the reset signal when exlvi v exlvi . generates an internal interrupt signal when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). remark lvisel: bit 2 of low-vo ltage detection register (lvim) lvimd: bit 1 of lvim while the low-voltage detector is operati ng, whether the supply vo ltage or the input voltage from an external input pin is more than or less than the detec tion level can be checked by reading the low-voltage detection flag (lvif: bit 0 of lvim). when the low-voltage detector is used to re set, bit 0 (lvirf) of the reset control flag register (resf) is set to 1 if reset occurs. for details of resf, see chapter 14 reset function . chapter 16 low-voltage detector user?s manual u18685ej3v0ud 307 16.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown in figure 16-1. figure 16-1. block diagram of low-voltage detector lvis1 lvis0 lvion ? + reference voltage source v dd internal bus n-ch low-voltage detection level selection register (lvis) low-voltage detection register (lvim) lvis2 lvis3 lvif intlvi internal reset signal 4 lvisel exlvi/p120/ intp0 lvimd v dd low-voltage detection level selector selector selector 16.3 registers controlling low-voltage detector the low-voltage detector is contro lled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level se lection register (lvis) ? port mode register 12 (pm12) (1) low-voltage detection register (lvim) this register sets low-volt age detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. the generation of a reset signal other than an lvi reset clears this register to 00h. chapter 16 low-voltage detector user?s manual u18685ej3v0ud 308 figure 16-2. format of low-voltage detection register (lvim) <0> lvif <1> lvimd <2> lvisel 3 0 4 0 5 0 6 0 <7> lvion symbol lvim address: ffbeh after reset: 00h note 1 r/w note 2 lvion notes 3, 4 enables low-voltage detection operation 0 disables operation 1 enables operation lvisel note 3 voltage detection selection 0 detects level of supply voltage (v dd ) 1 detects level of input voltage from external input pin (exlvi) lvimd note 3 low-voltage detection operation m ode (interrupt/reset) selection 0 ? lvisel = 0: generates an internal interrupt signal when the supply voltage (v dd ) drops lower than the detection voltage (v lvi ) (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). ? lvisel = 1: generates an interrupt si gnal when the input voltage from an external input pin (exlvi) drops lower than the detection voltage (v exlvi ) (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). 1 ? lvisel = 0: generates an internal reset signal when the supply voltage (v dd ) < detection voltage (v lvi ) and releases the reset signal when v dd v lvi . ? lvisel = 1: generates an internal reset signal when the input voltage from an external input pin (exlvi) < detection voltage (v exlvi ) and releases the reset signal when exlvi v exlvi . lvif note 4 low-voltage detection flag 0 ? lvisel = 0: supply voltage (v dd ) detection voltage (v lvi ), or when operation is disabled ? lvisel = 1: input voltage from external input pin (exlvi) detection voltage (v exlvi ), or when operation is disabled 1 ? lvisel = 0: supply voltage (v dd ) < detection voltage (v lvi ) ? lvisel = 1: input voltage from external input pin (exlvi) < detection voltage (v exlvi ) notes 1. this bit is cleared to 00h upon a reset other than an lvi reset. 2. bit 0 is read-only. 3. lvion, lvimd, and lvisel are cleared to 0 in the case of a reset other than an lvi reset. these are not cleared to 0 in the case of an lvi reset. 4. when lvion is set to 1, operation of the com parator in the lvi circ uit is started. use software to wait for an operation stabilization time (10 s (max.)) from when lvion is set to 1 until operation is stabilized. a fter operation has stabilized, 50 s (typ.) are required from when a state below lvi detection voltage has been entered, until lvif is set (1). cautions 1. to stop lvi, follow ei ther of the procedures below. ? when using 8-bit memory manipulati on instruction: write 00h to lvim. ? when using 1-bit memory manipulati on instruction: clear lvion to 0. 2. input voltage from external input pin (exlvi) must be exlvi < v dd . 3. after an lvi reset has been generated, do not write values to lvis and lvim when lvion = 1. 4. when using lvi as an interrupt, if lvion is cleared (0) in a state below the lvi detection voltage, an intlvi signal is generated and lviif becomes 1. chapter 16 low-voltage detector user?s manual u18685ej3v0ud 309 (2) low-voltage detection level selection register (lvis) this register selects the low-volt age detection level of supply voltage (v dd ). when an input voltage from the ex ternal input pin (exlvi) is detected, the det ection voltage (v exlvi = 1.21 v (typ.)) is fixed. therefore, se tting of lvis is not necessary. this register can be set by a 1-bit or 8-bit memory manipulation instruction. the generation of a reset signal other than an lvi reset clears this register to 00h. figure 16-3. format of low-voltage det ection level selection register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 lvis3 4 0 5 0 6 0 7 0 symbol lvis address: ffbfh after reset: 00h note 1 r/w lvis3 lvis2 lvis1 lvis0 detection level other than below setting prohibited 0 1 0 1 v lvi5 (3.47 v 0.1 v) 0 1 1 0 v lvi6 (3.32 v 0.1 v) 0 1 1 1 v lvi7 (3.16 v 0.1 v) 1 0 0 0 v lvi8 (3.01 v 0.1 v) 1 0 0 1 v lvi9 (2.85 v 0.1 v) 1 0 1 0 v lvi10 (2.70 v 0.1 v) 1 0 1 1 v lvi11 (2.55 v 0.1 v) 1 1 0 0 v lvi12 (2.39 v 0.1 v) 1 1 0 1 v lvi13 (2.24 v 0.1 v) 1 1 1 0 v lvi14 (2.05 v 0.05 v) 1 1 1 1 v lvi15 (1.93 v 0.1 v) note the value of lvis is not reset but retained as is, upon a reset by lvi. it is cleared to 00h upon other resets. cautions 1. be sure to cl ear bits 4 to 7 to ?0?. 2. do not change the value of lvis during lvi operation. 3. after an lvi reset has been generated, do not write values to lvis and lvim when lvion = 1. chapter 16 low-voltage detector user?s manual u18685ej3v0ud 310 (3) port mode register 12 (pm12) when using the p120/exlvi/intp0 pin for external low- voltage detection potential inpu t, set pm120 to 1. at this time, the output latch of p120 may be 0 or 1. pm12 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm12 to ffh. figure 16-4. format of port mode register 12 (pm12) address: ff2ch after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm12 1 1 1 1 1 pm122 pm121 pm120 pm12n p12n pin i/o mode selection (n = 0 to 2) 0 output mode (output buffer on) 1 input mode (output buffer off) 16.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. (1) used as reset (lvimd = 1) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ), generates an internal reset signal when v dd < v lvi , and releases internal reset when v dd v lvi . ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v (typ.)), generates an internal reset signal when exlvi < v exlvi , and releases internal reset when exlvi v exlvi . (2) used as interrupt (lvimd = 0) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ). when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ), generates an interrupt signal (intlvi). ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v (typ.)). when exl vi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ), generates an interrupt signal (intlvi). while the low-voltage detector is operati ng, whether the supply vo ltage or the input voltage from an external input pin is more than or less than the detec tion level can be checked by reading the low-voltage detection flag (lvif: bit 0 of lvim). remark lvimd: bit 1 of low-volt age detection register (lvim) lvisel: bit 2 of lvim chapter 16 low-voltage detector user?s manual u18685ej3v0ud 311 16.4.1 when used as reset (1) when detecting level of supply voltage (v dd ) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low- voltage detection register (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvi s3 to lvis0) of the low-voltage detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for an operation stabilization time (10 s (max.)). <6> wait until it is che cked that (supply voltage (v dd ) detection voltage (v lvi )) by bit 0 (lvif) of lvim. <7> set bit 1 (lvimd) of lvim to 1 (gener ates reset when the level is detected). figure 16-5 shows the timing of the internal rese t signal generated by the lo w-voltage detector. the numbers in this timing chart correspond to <1> to <7> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <4>. 2. if supply voltage (v dd ) detection voltage (v lvi ) when lvimd is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. chapter 16 low-voltage detector user?s manual u18685ej3v0ud 312 figure 16-5. timing of low-voltage det ector internal reset signal generation (detects level of supply voltage (v dd )) supply voltage (v dd ) <3> <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <4> <7> clear clear clear <5> wait time lvion flag (set by software) lvimd flag (set by software) h note 1 l lvisel flag (set by software) <6> <2> v lvi v poc = 1.8 v (typ.) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag r egister (resf). for details of resf, see chapter 14 reset function . remark <1> to <7> in figure 16-5 above correspond to <1 > to <7> in the description of ?when starting operation? in 16.4.1 (1) when detecting level of supply voltage (v dd ) . chapter 16 low-voltage detector user?s manual u18685ej3v0ud 313 (2) when detecting level of input voltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regi ster (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for an operation stabilization time (10 s (max.)). <5> wait until it is check ed that (input voltage from ex ternal input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.))) by bit 0 (lvif) of lvim. <6> set bit 1 (lvimd) of lvim to 1 (generat es reset signal when the level is detected). figure 16-6 shows the timing of the internal rese t signal generated by the lo w-voltage detector. the numbers in this timing chart correspond to <1> to <6> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <3>. 2. if input voltage from external input pin (exlvi) detection voltage (vexlvi = 1.21 v (typ.)) when lvimd is set to 1, an in ternal reset signal is not generated. 3. input voltage from external input pin (exlvi) must be exlvi v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. chapter 16 low-voltage detector user?s manual u18685ej3v0ud 314 figure 16-6. timing of low-voltage det ector internal reset signal generation (detects level of input voltage fr om external input pin (exlvi)) input voltage from external input pin (exlvi) lvi detection voltage (v exlvi ) <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <3> <6> lvion flag (set by software) lvimd flag (set by software) h note 1 lvisel flag (set by software) <5> <2> not cleared not cleared <4> wait time not cleared not cleared not cleared notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag r egister (resf). for details of resf, see chapter 14 reset function . remark <1> to <6> in figure 16-6 above correspond to <1> to <6> in the description of ? when starting operation? in 16.4.1 (2) when detecting level of input voltage from external input pin (exlvi) . chapter 16 low-voltage detector user?s manual u18685ej3v0ud 315 16.4.2 when used as interrupt (1) when detecting level of supply voltage (v dd ) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low- voltage detection register (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvi s3 to lvis0) of the low-voltage detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for an operation stabilization time (10 s (max.)). <6> confirm that ?supply voltage (v dd ) detection voltage (v lvi )? when detecting the falling edge of v dd , or ?supply voltage (v dd ) < detection voltage (v lvi )? when detecting the rising edge of v dd , at bit 0 (lvif) of lvim. <7> clear the interrupt request flag of lvi (lviif) to 0. <8> release the interrupt mask flag of lvi (lvimk). <9> clear bit 1 (lvimd) of lvim to 0 (generates in terrupt signal when the leve l is detected) (default value). <10> execute the ei instruction (when vector interrupts are used). figure 16-7 shows the timing of t he interrupt signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <9> above. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. chapter 16 low-voltage detector user?s manual u18685ej3v0ud 316 figure 16-7. timing of low-voltage de tector interrupt signal generation (detects level of supply voltage (v dd )) supply voltage (v dd ) time <1> note 1 <8> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag internal reset signal <4> <6> <7> cleared by software <5> wait time lvion flag (set by software) note 2 note 2 <3> l lvisel flag (set by software) <2> lvimd flag (set by software) l <9> v lvi v poc = 1.8 v (typ.) note 2 note 3 note 3 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvion is cleared (0) in a state below the lv i detection voltage, an intl vi signal is generated and lviif becomes 1. remark <1> to <9> in figure 16-7 above correspond to <1 > to <9> in the description of ?when starting operation? in 16.4.2 (1) when detecting level of supply voltage (v dd ) . chapter 16 low-voltage detector user?s manual u18685ej3v0ud 317 (2) when detecting level of input voltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regi ster (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for an operation stabilization time (10 s (max.)). <5> confirm that ?input voltage fr om external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)? when detecting the falling edge of exlvi, or ?i nput voltage from external input pin (exlvi) < detection voltage (v exlvi = 1.21 v (typ.)? when detecting the risi ng edge of exlvi, at bit 0 (lvif) of lvim. <6> clear the interrupt request flag of lvi (lviif) to 0. <7> release the interrupt mask flag of lvi (lvimk). <8> clear bit 1 (lvimd) of lvim to 0 (generates in terrupt signal when the leve l is detected) (default value). <9> execute the ei instruction (when vector interrupts are used). figure 16-8 shows the timing of t he interrupt signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <8> above. caution input voltage from external input pin (exlvi) must be exlvi v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. chapter 16 low-voltage detector user?s manual u18685ej3v0ud 318 figure 16-8. timing of low-voltage detector interrupt signal generation (detects level of input voltage fr om external input pin (exlvi)) input voltage from external input pin (exlvi) v exlvi time <1> note 1 <7> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag <3> <5> <6> cleared by software <4> wait time lvion flag (set by software) note 2 note 2 lvisel flag (set by software) <2> lvimd flag (set by software) l <8> note 2 note 3 note 3 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvion is cleared (0) in a state below the lv i detection voltage, an intl vi signal is generated and lviif becomes 1. remark <1> to <8> in figure 16-8 above correspond to <1 > to <8> in the description of ?when starting operation? in 16.4.2 (2) when detecting level of input voltage from external input pin (exlvi) . chapter 16 low-voltage detector user?s manual u18685ej3v0ud 319 16.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and re leased from the reset status. in this case, the time from release of reset to the st art of the operation of the mi crocontroller can be arbitrarily set by taking action (1) below. (2) when used as interrupt interrupt requests may be frequently generat ed. take (b) of action (2) below. chapter 16 low-voltage detector user?s manual u18685ej3v0ud 320 figure 16-9. example of software processing after reset release (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage ; check the reset source note initialize the port. reset initialization processing <1> 50 ms have passed? (tmifh1 = 1?) initialization processing <2> setting 8-bit timer h1 (to measure 50 ms) ; setting of division ratio of system clock, such as setting of timer yes no clearing wdt detection voltage or higher (lvif = 0?) yes restarting timer h1 (tmhe1 = 0 tmhe1 = 1) no ; the timer counter is cleared and the timer is started. lvi reset ;f prs = internal high-speed oscillation clock (4 mhz (max.)) (default) source: f prs (4 mhz (max.))/2 12 , where comparison value = 49: ? 50 ms timer starts (tmhe1 = 1). note a flowchart is shown on the next page. chapter 16 low-voltage detector user?s manual u18685ej3v0ud 321 figure 16-9. example of software processing after reset release (2/2) ? checking reset source yes: reset generation by lvi no: reset generation other than by lvi set lvi (set lvim and lvis registers) check reset source lvion of lvim register = 1? chapter 16 low-voltage detector user?s manual u18685ej3v0ud 322 16.6 ram data retention detector by using this circuit, it is possible to judge whether power supply (v dd ) drops below than the voltage which can not retain the data value of ram when battery is changed. the ram data retenti on detection voltage (v ld ) is 1.4v +/- 0.1v. the ram data retention detector is c ontrolled by the following registers. ? ram data retention control register (lvdet) (1) ram data retention c ontrol register (lvdet) this register sets ram data retent ion detection and t he operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. figure 16-10. format of ram data re tention control register (lvdet) address: ffb0h after reset : undefined note r/w symbol 7 6 5 4 3 2 1 0 lvdet 0 0 0 0 0 0 lvdet0 0 lvdet0 ram data retention flag 0 ram data may change 1 ram data are retained note when v dd is below than v ld (1.4v(typ.)), the value becomes ? 00h?. in other case, the vvalue of lvdet will be remained. when ram data retenti on detector function is used, please set lvdet0 to ?1?. ram data retention flag will be cleared to ?0? when the power supply (v dd ) drops below than ram data retention detect voltage (v ld :1.4+/-0.1 v). it is possible to judge whether ram data value are remai ned by checking ram data retention flag (lvdet0) after reset. user?s manual u18685ej3v0ud 323 chapter 17 option byte 17.1 functions of option bytes the flash memory at 0080h to 0084h of the pd179f11x, 179f12x microcontroller is an option byte area. when power is turned on or when the device is restarted from the reset status, t he device automatically references the option bytes and sets specified function s. when using the product, be sure to se t the following functions by using the option bytes. caution be sure to set 00h to 0081h and 0083h. (1) 0080h { internal low-speed oscillator operation ? can be stopped by software ? cannot be stopped { watchdog timer interval time setting { watchdog timer counter operation ? enabled counter operation ? disabled counter operation { watchdog timer window open period setting (2) 0084h { on-chip debug operation control ? disabling on-chip debug operation ? enabling on-chip debug operation and erasing data of th e flash memory in case authentication of the on- chip debug security id fails ? enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of the on-chip debug security id fails chapter 17 option byte user?s manual u18685ej3v0ud 324 17.2 format of option byte the format of the option byte is shown below. figure 17-1. format of option byte (1/2) address: 0080h 7 6 5 4 3 2 1 0 0 window1 window0 wdton wdcs2 wdcs1 wdcs0 lsrosc window1 window0 watchdog timer window open period 0 0 25% 0 1 50% 1 0 75% 1 1 100% wdton operation control of watchdog ti mer counter/illegal access detection 0 counter operation disabled (counting stopped afte r reset), illegal access detection operation disabled 1 counter operation enabled (counting started after reset), illegal access detection operation enabled wdcs2 wdcs1 wdcs0 watc hdog timer overflow time 0 0 0 2 10 /f rl (3.41 ms) 0 0 1 2 11 /f rl (6.83 ms) 0 1 0 2 12 /f rl (13.65 ms) 0 1 1 2 13 /f rl (27.31 ms) 1 0 0 2 14 /f rl (54.61 ms) 1 0 1 2 15 /f rl (109.23 ms) 1 1 0 2 16 /f rl (218.45 ms) 1 1 1 2 17 /f rl (436.91 ms) lsrosc internal low-speed oscillator operation 0 can be stopped by software (stopped when 1 is written to bit 1 (lsrstop) of rcm register) 1 cannot be stopped (not stopped even if 1 is written to lsrstop bit) cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer continues its operati on during self programming of the flash memory. during processing, the interrupt acknowledge time is delayed. set the overflow time and window size taking this delay into consideration. 3. if lsrosc = 0 (oscillation can be stopped by software), the count clock is not supplied to the watchdog timer in the halt and stop modes, rega rdless of the setting of bit 1 (lsrstop) of the internal oscillation mode register (rcm). when 8-bit timer h1 operates with the internal low-speed oscillation clo ck, the count clock is supplied to 8-bit timer h1 even in the halt/stop mode. 4. be sure to clear bit 7 to 0. remarks 1. f rl : internal low-speed oscillation clock frequency 2. ( ): f rl = 300 khz (max.) chapter 17 option byte user?s manual u18685ej3v0ud 325 figure 17-1. format of option byte (2/2) address: 0081h to 0083h note 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 note be sure to set 00h to 0081h and 0083h, as these addresses are reserved areas. address: 0084h note 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ocden1 ocden0 ocden1 ocden0 on-chip debug operation control 0 0 operation disabled 0 1 setting prohibited 1 0 operation enabled. does not erase data of the flash memory in case authentication of the on-chip debug security id fails. 1 1 operation enabled. erases data of the flash memory in case authentication of the on-chip debug security id fails. note to use the on-chip debug function, set 02h or 03h to 0084h. remark for the on-chip debug security id, see chapter 19 on-chip debug function . here is an example of description of t he software for setting the option bytes. opt cseg at 0080h option: db 30h ; enables watchdog timer operation (illegal access detection operation), ; window open period of watchdog timer: 50%, ; overflow time of watchdog timer: 2 10 /f rl , ; internal low-speed oscillator can be stopped by software. db 00h ; reserved area db 00h ; reserved area db 00h ; on-chip debug operation disabled remark referencing of the option byte is performed during reset processing. for the reset processing timing, see chapter 14 reset function . user?s manual u18685ej3v0ud 326 chapter 18 flash memory the pd179f11x, 179f12x microcontrollers in corporate the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 18.1 internal memory size switching register the internal memory capacity can be selected using the internal memory size switching register (ims). ims is set by an 8-bit memory manipulation instruction. reset signal generation sets ims to cfh. caution be sure to set each product to the valu es shown in table 18-1 after a reset release. figure 18-1. format of internal memo ry size switching register (ims) address: fff0h after reset: cfh r/w symbol 7 6 5 4 3 2 1 0 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal high-speed ram capacity selection 0 0 0 768 bytes 0 1 0 512 bytes 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 inte rnal rom capacity selection 0 0 0 1 4 kb 0 0 1 0 8 kb 0 1 0 0 16 kb 0 1 1 0 24 kb 1 0 0 0 32 kb other than above setting prohibited table 18-1. internal memory si ze switching register settings flash memory versions ( pd179f11x, 179f12x microcontroller) ims setting pd179f110 41h pd179f111 42h pd179f112, 179f122 04h pd179f113, 179f123 c6h pd179f114, 179f124 c8h chapter 18 flash memory user?s manual u18685ej3v0ud 327 18.2 writing with flash memory programmer data can be written to the flash memory on-board or o ff-board, by using a dedicated flash memory programmer. (1) on-board programming the contents of the flash memo ry can be rewritten after the pd179f11x, 179f12x microcontrollers have been mounted on the target system. t he connectors that connect the dedi cated flash memory programmer must be mounted on the target system. (2) off-board programming data can be written to the flash memory with a dedicated program adapter (fa series) before the pd179f11x, 179f12x microcontrollers are mounted on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. table 18-2. example of wiring between pd179f11x microcontroller and dedicated flash memory programmer pin configuration of dedicated flash memory programmer pd179f11x microcontroller signal name i/o pin function pin name pin no. si/rxd input receive signal txd6/p13 29 so/txd output transmit signal rxd6/p14 28 sck output transfer clock ? ? clk output clock to pd179f11x, 179f12x microcontroller note note /reset output reset signal reset 6 flmd0 output mode signal flmd0 9 v dd 14 v dd i/o v dd voltage generation/ power monitoring av ref 33 v ss 13 gnd ? ground av ss 34 note only the x1 clock (f x ) or external main system clock (f exclk ) can be used. when using the clock output of the dedicated flash memory programmer, pin connection varies depending on the type of the dedicated flash memory programmer used. ? pg-fp4, fl-pr4, pg-fp5, fl-pr5: connect clk of the programmer to exclk/x2/p122/ocd0b (pin 10). chapter 18 flash memory user?s manual u18685ej3v0ud 328 examples of the recommended connecti on when using the adapter for flash memory writing are shown below. figure 18-2. example of wiring adapter fo r flash memory writing (30-pin products) gnd vdd si so sck clk /reset writer interface flmd0 gnd v dd (1.8 to 3.6 v) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 remark the above figure illustrates an exampl e of wiring when using the clock output from the pg-fp4, fl-pr4, pg-fp5 or fl-pr5. chapter 18 flash memory user?s manual u18685ej3v0ud 329 18.3 programming environment the environment required for writing a program to t he flash memory of the pd179f11x, 179f12x microcontrollers are illustrated below. figure 18-3. environment for wr iting program to flash memory rs-232c usb flmd0 v dd v ss reset uart6 host machine dedicated flash memory programmer 179f11x, 179f12x microcontrollers pg-fp5 start power pa s s busy ng a host machine that controls the dedicat ed flash memory programmer is necessary. to interface between the dedicated flash memory programmer and the pd179f11x, 179f12x microcontroller, csi10 or uart6 is used for manipulati on such as writing and erasing. to write the flash memory off-board, a dedicated program adapter (fa series) is necessary. 18.4 communication mode communication between the dedicated flash memory programmer and the pd179f11x, 179f12x microcontrollers are established by serial communication of the pd179f11x, 179f12x microcontrollers. figure 18-4. communication with de dicated flash memory programmer transfer rate: 115200 bps v dd v ss reset txd6 rxd6 v dd gnd /reset si/rxd so/txd exclk note clk note dedicated flash memory programmer flmd0 flmd0 179f11x, 179f12x microcontrollers pg-fp5 start power pass busy ng note the above figure illustrates an exampl e of wiring when using the clock output from the pg-fp4, fl-pr4, pg-fp5 or fl-pr5. chapter 18 flash memory user?s manual u18685ej3v0ud 330 the dedicated flash memory programmer generates the following signals for the pd179f11x, 179f12x microcontroller. for details, refer to the user?s manual for the pg-fp4 or fl-pr4. table 18-3. pin connection dedicated flash memory programmer pd179f11x, 179f12x microcontrollers signal name i/o pin function pin name connection flmd0 output mode signal flmd0 v dd i/o v dd voltage generation/power monitoring v dd , av ref gnd ? ground v ss , av ss clk output clock output to pd179f11x, 179f12x microcontroller note 1 { note 1 /reset output reset signal reset si/rxd input receive signal so10/txd6 so/txd output transmit signal si10/rxd6 sck output transfer clock sck10 note only the x1 clock (f x ) or external main system clock (f exclk ) can be used. when using the clock output of the dedicated flash memory programmer, pin connection varies depending on the type of the dedicated flash memory programmer used. ? pg-fp4, fl-pr4, pg-fp5, fl-pr5: connect clk of the programmer to exclk/x2/p122. remark : be sure to connect the pin. { : the pin does not have to be connected if the signal is generated on the target board. : the pin does not have to be connected. 18.5 handling of pins on board to write the flash memory on-board, connectors that connect the dedicat ed flash memory programmer must be provided on the target system. first provide a function that selects the normal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pi ns not used for programming the flash memory are in the same status as immediately after re set. therefore, if the ex ternal device does not recogni ze the state immediately after reset, the pins must be handled as described below. 18.5.1 flmd0 pin in the normal operation mode, 0 v is input to the flmd0 pin. in the flash memory programming mode, the v dd write voltage is supplied to the flmd0 pin. an flmd0 pin connection example is shown below. chapter 18 flash memory user?s manual u18685ej3v0ud 331 figure 18-5. flmd0 pin connection example flmd0 100 k ? (recommended) dedicated flash memory programmer connection pin 179f11x, 179f12x microcontrollers 18.5.2 serial interface pins the pins used by each serial interface are listed below. table 18-4. pins used by each serial interface serial interface pins used uart6 txd6, rxd6 to connect the dedicated flash memory programmer to the pi ns of a serial interface that is connected to another device on the board, care must be exer cised so that signals do not collide or that the other device does not malfunction. (1) signal collision if the dedicated flash memory programmer (output) is connected to a pin (input) of a serial interface connected to another device (out put), signal collision takes place. to av oid this collision, either isolate the connection with the other device, or make the other device go in to an output high- impedance state. figure 18-6. signal collision (input pin of serial interface) input pin signal collision dedicated flash memory programmer connection pin other device output pin in the flash memory programming mode, the signal output by the device collides with the signal sent from the dedicated flash memory programmer. therefore, isolate the signal of the other device. 179f11x, 179f12x microcontrollers (2) malfunction of other device if the dedicated flash memory programme r (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to t he other device, c ausing the device to malfunction. to avoid this malfunction, isolate the connection with the other device. chapter 18 flash memory user?s manual u18685ej3v0ud 332 figure 18-7. malfunction of other device pin dedicated flash memory programmer connection pin other device input pin if the signal output by the 179f11x, 179f12x microcontrollers in the flash memory programming mode affects the other device, isolate the signal of the other device. pin dedicated flash memory programmer connection pin other device input pin if the signal output by the dedicated flash memory programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. 179f11x, 179f12x microcontrollers 179f11x, 179f12x microcontrollers 18.5.3 reset pin if the reset signal of the dedicated flash memory programme r is connected to the reset pin that is connected to the reset signal generator on the board, si gnal collision takes place. to prevent this collision, isolate the connection with the reset signal generator. if the reset signal is input from the user system while t he flash memory programming mode is set, the flash memory will not be correctly programmed. do not input any signal other than the reset signal of the dedicated flash memory programmer. figure 18-8. signal collision (reset pin) reset dedicated flash memory programmer connection signal reset signal generator signal collision output pin in the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash memory programmer. therefore, isolate the signal of the reset signal generator. 179f11x, 179f12x microcontrollers chapter 18 flash memory user?s manual u18685ej3v0ud 333 18.5.4 port pins when the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately afte r reset. if external devices connected to the ports do not recognize the port status immediately after reset, t he port pin must be connected to v dd or v ss via a resistor. 18.5.5 regc pin connect the regc pin to g nd via a capacitor (0.47 f: recommended) in the same manner as during normal operation. 18.5.6 other signal pins connect x1 and x2 in the same status as in t he normal operation mode when using the on-board clock. to input the operating clock from the dedicated flash memory programmer, however, connect as follows. ? pg-fp4, fl-pr4, pg-fp5, fl-pr5: connect cl k of the programmer to exclk/x2/p122/ocd0b. caution only the x1 clock (f x ) or external main system clock (f exclk ) can be used. 18.5.7 power supply to use the supply voltage out put of the flash memory programmer, connect the v dd pin to v dd of the flash memory programmer, and the v ss pin to gnd of the flash memory programmer. to use the on-board supply voltage, connect in compliance with the normal operation mode. however, be sure to connect the v dd and v ss pins to v dd and gnd of the flash memo ry programmer to use the power monitor function with the flash memory progr ammer, even when using t he on-board supply voltage. chapter 18 flash memory user?s manual u18685ej3v0ud 334 18.6 programming method 18.6.1 controlling flash memory the following figure illustrates the proc edure to manipulate the flash memory. figure 18-9. flash memory manipulation procedure start selecting communication mode manipulate flash memory end? yes flmd0 pulse supply no end flash memory programming mode is set 18.6.2 flash memory programming mode to rewrite the contents of the fl ash memory by using the dedicated flash memory programmer, set the pd179f11x, 179f12x microcontroller in the flash memory programming mode. to set the mode, set the flmd0 pin to v dd and clear the reset signal. change the mode by using a jumper when writing the flash memory on-board. figure 18-10. flash memory programming mode v dd reset 5.5 v 0 v v dd 0 v flash memory programming mode flmd0 flmd0 pulse v dd 0 v table 18-5. relationship between flmd0 pi n and operation mode after reset release flmd0 operation mode 0 normal operation mode v dd flash memory programming mode chapter 18 flash memory user?s manual u18685ej3v0ud 335 18.6.3 selecting communication mode in the pd179f11x, 179f12x microcontrollers, a communication mode is selected by inputting pulses to the flmd0 pin after the dedicated flash memory programming mode is entered. these fl md0 pulses are generated by the flash memory programmer. the following table shows the relationship betw een the number of pulses and communication modes. table 18-6. communication modes standard setting note 1 communication mode port speed frequency multiply rate pins used periphera l clock number of flmd0 pulses uart-ext-osc f x 0 uart (uart6) uart-ext-fp4ck 115,200 bps note 3 2 to 4 mhz note 2 1.0 txd6, rxd6 f exclk 3 notes 1. selection items for standard settings on gu i of the flash memory programmer. 2. the possible setting range differs depending on the voltage. for details, refer to the chapter of electrical specifications. 3. because factors other than the baud ra te error, such as the signal wa veform slew, also affect uart communication, thoroughly evaluate the sl ew as well as the baud rate error. caution the receive clock is calcula ted based on the reset command sent fr om the dedicated flash memory programmer after the flmd0 pulse has been received. remark f x : x1 clock f exclk : external main system clock f rh : internal high-speed oscillation clock 18.6.4 communication commands the pd179f11x, 179f12x microcontrollers co mmunicate with the dedicated flas h memory programmer by using commands. the signals sent from t he flash memory programmer to the pd179f11x, 179f12x microcontrollers are called commands, and the signals sent from the pd179f11x, 179f12x microcontrolle rs to the dedicated flash memory programmer are called response. figure 18-11. communication commands command response dedicated flash programmer 179f11x, 179f12x microcontrollers pg-fp5 start power pass busy ng the flash memory control commands of the pd179f11x, 179f12x microcontrollers ar e listed in the table below. all these commands are issued from the programmer and the pd179f11x, 179f12x microcontrollers perform processing corresponding to the respective commands. chapter 18 flash memory user?s manual u18685ej3v0ud 336 table 18-7. flash memory control commands classification command name function verify verify compares the contents of a specified area of the flash memory with data transmitted from the programmer. erase block erase erases a ll area in the flash memory. blank check block blank check checks if a specif ied block in the flash memory has been correctly erased. write programming writes data to a s pecified area in the flash memory. status gets the current operating status (status data). silicon signature gets the device information (such as the part number and flash memory configuration). version get gets the device ve rsion and firmware version. getting information checksum gets the checksum data for a specified area. security security set sets security information. reset used to detect synchroniza tion status of communication. others oscillating frequency set specifies an oscillation frequency. the pd179f11x, 179f12x microcontroller returns a respons e for the command issued by the dedicated flash memory programmer. the re sponse names sent from the pd179f11x, 179f12x microcontro llers are listed below. table 18-8. response names response name function ack acknowledges command/data. nak acknowledges illegal command/data. 18.7 security settings the pd179f11x, 179f12x microcontrollers support a security f unction that prohibits rewr iting the user program written to the internal flash memory, so that the program cannot be c hanged by an unauthorized person. the operations shown below can be perfo rmed using the security set command. the security setting is valid when the programming mode is set next. ? disabling batch erase (chip erase) setting prohibited for pd179f11x, 179f12x microcontrollers. ? disabling block erase execution of the block erase command fo r a specific block in the flash me mory is prohibited during on-board/off- board programming. however, blocks can be erased by means of self programming. ? disabling write execution of the write and block eras e commands for entire blocks in the fl ash memory is prohibited during on- board/off-board programming. however, blocks c an be written by means of self programming. chapter 18 flash memory user?s manual u18685ej3v0ud 337 ? disabling rewriting block 00h to block 03h execution of the block erase comm and, and write command on 00h to block 03h (0000h to 0fffh) in the flash memory is prohibited by this setting. caution if a security setting that re writes block 00h to block 03h has b een applied, block 00h to block 03h of that device will not be rewritten. the block erase, and write commands are enabled by the default setting when the flash memory is shipped. security can be set by on-board/off-board programming. each security setting can be used in combination. security setting can not be changed if once security prohibition setting is set for pd179f11x, 179f12x microcontrollers table 18-9 shows the relationship betw een the erase and writ e commands when the pd179f11x, 179f12x microcontrollers? security function is enabled. table 18-9. relationship between enabling security function and command (1) during on-board/off-board programming executed command valid security block erase note write prohibition of block erase can be performed. prohibition of writing cannot be performed. prohibition of rewriting block 00h to block 03h blocks cannot be erased. boot cluster 0 cannot be written. note the block erase command erases all blocks in a batch when in on-board or off-board programming mode. (2) during self programming executed command valid security block erase note write prohibition of block erase prohibition of writing blocks can be erased. can be performed. prohibition of rewriting block 00h to block 03h boot cluster 0 cannot be eras ed. boot cluster 0 cannot be written. note the block erase command can be used to erase blocks in one-block (1 kb) units when in self programming mode. chapter 18 flash memory user?s manual u18685ej3v0ud 338 table 18-10 shows how to perform security settings in each programming mode. table 18-10. setting security in each programming mode (1) on-board/off-board programming security security setting how to disable security setting prohibition of block erase prohibition of writing prohibition of rewriting block 00h to block 03h set via gui of dedicated flash memory programmer, etc. cannot be disabled after set. (2) self programming security security setting how to disable security setting prohibition of block erase prohibition of writing prohibition of rewriting block 00h to block 03h cannot be set. cannot be disabled after set. chapter 18 flash memory user?s manual u18685ej3v0ud 339 18.8 flash memory programming by self-programming the pd179f11x, 179f12x microcontrollers s upports a self programming function that can be used to rewrite the flash memory via a user program. because this function allows a user application to rewrit e the flash memory by using a self programming library, it can be us ed to upgrade the program in the field. if an interrupt occurs during self programming, self pr ogramming can be temporarily stopped and interrupt servicing can be executed. to execute interrupt servicing, restore the normal operat ion mode after self programming has been stopped, and execute the ei inst ruction. after the self programming mode is later restored, self programming can be resumed. remark for details of the self progra mming function and self programming library, refer to 78k0 microcontroller self-programming library ty pe01 user?s manual (u18274e). cautions 1. input a high level to the flmd0 pin during self programming. (1) setting by external input ? set fpen0 (flmd0 pull-up/pull-down enab le register (fpen) bit 0) to ?0?. ? input high-level to flmd0 (100kohm pull-down) (2) setting by internal pull-up resistor ? pull-down flmd0 pin via 100kohm. ? set fpen0 (flmd0 pull-up/pull-down enable register (fpen) bit 0) and flmdpup (flmd0 pul-up/pull-down control register (fpctl) bit 0) to ?1?. by setting them, input level of flmd0 pin becomes ?high?. figure 18-12. flmd0 pin se tting when self programming flmd0 flmpup internal signal 179f11x, 179f12x 0:pull-down 1:pull-up fpen0 0:disable 1:enable 100 k ? (recommended) chapter 18 flash memory user?s manual u18685ej3v0ud 340 figure 18-13. format of flmd0 pull-up/ pull-down control register (fpctl) address: ff35h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 fpctl 0 0 0 0 0 0 0 flmdpup flmdpup flmd0 pull-up/pull-down setting 0 pull-down 1 pull-up figure 18-14. format of flmd0 pull- up/pull-down enable register (fpen) address: ff37h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 fpen 0 0 0 0 0 0 0 fpen0 fpen0 flmd0 pull-up/pull-down enable setting 0 disable pull-up/pull-down 1 enable pull-up/pull-down cautions 2. be sure to execute the di in struction before starting self programming. the self programming function checks the interrupt request flags (if0l, if0h, if1l). if an interrupt request is generate d, self programming is stopped. 3. self programming is also st opped by an interrupt request th at is not masked even in thedi status. to prevent this, mask the interrupt by using the interrupt mask flag registers (mk0l, mk0h, mk1l). chapter 18 flash memory user?s manual u18685ej3v0ud 341 the following figure illustrates a flow of rewriting t he flash memory by using a self programming library. figure 18-15. flow of self pr ogramming (rewriting flash memory) remark for details of the self programming library, refer to 78k0 microcontroller sel f-programming library type01 user?s manual (u18274e) . flashblockblankcheck flashen v flashblockerase flashwordwrite setting operating environment normal completion ? flashstart yes no flashblockverif y no start of self programming checkflmd yes flashblockerase flashwordwrite flashblockverif y end of self programming flashend normal com p letion error no yes normal completion ? normal completion ? flmd0 pin high level low level flmd0 pin low level high level user?s manual u18685ej3v0ud 342 chapter 19 on-chip debug function 19.1 connecting qb-mini2 the pd179f11x, 179f12x microc ontrollers use the v dd , flmd0, reset, ocd0a/x1 (or ocd1a/p04), ocd0b/x2 (or ocd1b/p05), and v ss pins to communicate with the host ma chine via an on-chip debug emulator (qb- mini2). whether ocd0a/x1 and o cd1a/p04, or ocd0b/x2 and ocd1 b/p05 are used can be selected. figure 19-1. connection example of qb-mini2 and pd179f11x, 179f12x microcontrollers (when ocd0a/x1 and ocd0b/x2 are used) v dd target device flmd0 x1/ocd0a x2 /ocd0b data clk flmd0 reset v dd reset_out gnd target connector gnd v dd v dd v dd gnd r.f.u. r.f.u. note 1 to 10 k ? (recommended) (open) (open) reset_in (open) note make pull-down resistor 100 k ? . cautions 1. input the clock from th e ocd0a/x1 pin during on-chip debugging. 2. when ocd0a/x1 and ocd0b/ x2 are used for ocd, the vo ltage level of ocd1a/p04 and ocd1b/p05 during reset have to be fi xed level (high-level or low-level). 3. because reset pin is used by qb-mini2, alternate function can not be used for emulation. chapter 19 on-chip debug function user?s manual u18685ej3v0ud 343 figure 19-2. connection example of qb-mini2 and pd179f11x, 179f12x microcontroller (when ocd1a/p04 and ocd1b/p05 are used) v dd target device flmd0 ocd1a/p04 ocd1b/p05 data clk flmd0 reset v dd reset_out gnd target connector gnd note 3 v dd v dd v dd gnd r.f.u. r.f.u. note 2 1 to 10 k ? (recommended) (open) (open) v dd 3 to 10 k ? (recommended) note 1 reset_in (open) notes 1. this is the processing of the pi n when ocd1b/p05 is set as the i nput port (to prevent the pin from being left opened when not connected to qb-mini2). 2. make pull-down resistor 100 k ? . 3. make pull-down resistor 10 k ? (recommended). cautions 1. when ocd1a/p04, o cd1b/p05 is used for on-chip debug, do not set p04 and p05 to output mode during on-ch ip debug mode. 2. because reset pin is used by qb-mini2, alternate function can not be used for emulation. chapter 19 on-chip debug function user?s manual u18685ej3v0ud 344 19.2 reserved area used by qb-mini2 qb-mini2 uses the reserved areas show n in figure 19-3 below to implement communication with the target device, or each debug function. the shaded reserv ed areas are used for the respective debug functions to be used, and the other areas are always used for debugging. these reserv ed areas can be secured by using user programs and compiler options. for details on reserved area, refer to qb-mini2 user?s manual (u18371e) . figure 19-3. reserved area used by qb-mini2 debug monitor area (2 bytes) software break area (2 bytes) security id area (10 bytes) option byte area (1 byte) debug monitor area (257 bytes) pseudo rrm area (256 bytes) internal rom space internal ram space stack area for debugging (max. 16 bytes) 28fh 190h 18fh 8fh 8eh 85h 84h 7fh 7eh 03h 02h 00h remark shaded reserved areas: area used for the respective debug functions to be used other reserved areas: areas always used for debugging user?s manual u18685ej3v0ud 345 chapter 20 instruction set this chapter lists each instruction set of the pd179f11x, 179f12x microcontrollers in table form. for details of each operation and operation code, refer to the separate document 78k/0 series instructions user?s manual (u12326e) . 20.1 conventions used in operation list 20.1.1 operand identifier s and specification methods operands are written in the ?operand? column of each instruction in ac cordance with the specification method of the instruction operand identifier (refer to the assembler s pecifications for details). when there are two or more methods, select one of them. uppercase letters and the sym bols #, !, $ and [ ] are keywords and must be written as they are. each symbol has the following meaning. ? #: immediate data specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate num eric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register identifiers r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for specification. table 20-1. operand identifi ers and specification methods identifier specification method r rp sfr sfrp x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol note special function register symbol (16-bit manipulatable register even addresses only) note saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even address only) addr16 addr11 addr5 0000h to ffffh immediate data or labels (only even addresses for 16-bit da ta transfer instructions) 0800h to 0fffh immediate data or labels 0040h to 007fh immediate data or labels (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh c annot be accessed with these operands. remark for special function register symbols, see table 3-6 special function register list . chapter 20 instruction set user?s manual u18685ej3v0ud 346 20.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag ( ): memory contents indicated by addre ss or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ?? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 20.1.3 description of flag operation column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored chapter 20 instruction set user?s manual u18685ej3v0ud 347 20.2 operation list clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy r, #byte 2 4 ? r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 ? 7 sfr byte a, r note 3 1 2 ? a r r, a note 3 1 2 ? r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 ? 5 a sfr sfr, a 2 ? 5 sfr a a, !addr16 3 8 9 a (addr16) !addr16, a 3 8 9 (addr16) a psw, #byte 3 ? 7 psw byte a, psw 2 ? 5 a psw psw, a 2 ? 5 psw a a, [de] 1 4 5 a (de) [de], a 1 4 5 (de) a a, [hl] 1 4 5 a (hl) [hl], a 1 4 5 (hl) a a, [hl + byte] 2 8 9 a (hl + byte) [hl + byte], a 2 8 9 (hl + byte) a a, [hl + b] 1 6 7 a (hl + b) [hl + b], a 1 6 7 (hl + b) a a, [hl + c] 1 6 7 a (hl + c) mov [hl + c], a 1 6 7 (hl + c) a a, r note 3 1 2 ? a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 ? 6 a ? sfr a, !addr16 3 8 10 a ? (addr16) a, [de] 1 4 6 a ? (de) a, [hl] 1 4 6 a ? (hl) a, [hl + byte] 2 8 10 a ? (hl + byte) a, [hl + b] 2 8 10 a ? (hl + b) 8-bit data transfer xch a, [hl + c] 2 8 10 a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 20 instruction set user?s manual u18685ej3v0ud 348 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy rp, #word 3 6 ? rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 ? 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 ? 8 ax sfrp sfrp, ax 2 ? 8 sfrp ax ax, rp note 3 1 4 ? ax rp rp, ax note 3 1 4 ? rp ax ax, !addr16 3 10 12 ax (addr16) movw !addr16, ax 3 10 12 (addr16) ax 16-bit data transfer xchw ax, rp note 3 1 4 ? ax ? rp a, #byte 2 4 ? a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 ? a, cy a + r r, a 2 4 ? r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 a, cy a + (addr16) a, [hl] 1 4 5 a, cy a + (hl) a, [hl + byte] 2 8 9 a, cy a + (hl + byte) a, [hl + b] 2 8 9 a, cy a + (hl + b) add a, [hl + c] 2 8 9 a, cy a + (hl + c) a, #byte 2 4 ? a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 ? a, cy a + r + cy r, a 2 4 ? r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 a, cy a + (addr16) + c a, [hl] 1 4 5 a, cy a + (hl) + cy a, [hl + byte] 2 8 9 a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 a, cy a + (hl + b) + cy 8-bit operation addc a, [hl + c] 2 8 9 a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 20 instruction set user?s manual u18685ej3v0ud 349 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a, cy a ? byte saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte a, r note 3 2 4 ? a, cy a ? r r, a 2 4 ? r, cy r ? a a, saddr 2 4 5 a, cy a ? (saddr) a, !addr16 3 8 9 a, cy a ? (addr16) a, [hl] 1 4 5 a, cy a ? (hl) a, [hl + byte] 2 8 9 a, cy a ? (hl + byte) a, [hl + b] 2 8 9 a, cy a ? (hl + b) sub a, [hl + c] 2 8 9 a, cy a ? (hl + c) a, #byte 2 4 ? a, cy a ? byte ? cy saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte ? cy a, r note 3 2 4 ? a, cy a ? r ? cy r, a 2 4 ? r, cy r ? a ? cy a, saddr 2 4 5 a, cy a ? (saddr) ? cy a, !addr16 3 8 9 a, cy a ? (addr16) ? cy a, [hl] 1 4 5 a, cy a ? (hl) ? cy a, [hl + byte] 2 8 9 a, cy a ? (hl + byte) ? cy a, [hl + b] 2 8 9 a, cy a ? (hl + b) ? cy subc a, [hl + c] 2 8 9 a, cy a ? (hl + c) ? cy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) 8-bit operation and a, [hl + c] 2 8 9 a a (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 20 instruction set user?s manual u18685ej3v0ud 350 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) or a, [hl + c] 2 8 9 a a (hl + c) a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) xor a, [hl + c] 2 8 9 a a (hl + c) a, #byte 2 4 ? a ? byte saddr, #byte 3 6 8 (saddr) ? byte a, r note 3 2 4 ? a ? r r, a 2 4 ? r ? a a, saddr 2 4 5 a ? (saddr) a, !addr16 3 8 9 a ? (addr16) a, [hl] 1 4 5 a ? (hl) a, [hl + byte] 2 8 9 a ? (hl + byte) a, [hl + b] 2 8 9 a ? (hl + b) 8-bit operation cmp a, [hl + c] 2 8 9 a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 20 instruction set user?s manual u18685ej3v0ud 351 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy addw ax, #word 3 6 ? ax, cy ax + word subw ax, #word 3 6 ? ax, cy ax ? word 16-bit operation cmpw ax, #word 3 6 ? ax ? word mulu x 2 16 ? ax a x multiply/ divide divuw c 2 25 ? ax (quotient), c (remainder) ax c r 1 2 ? r r + 1 inc saddr 2 4 6 (saddr) (saddr) + 1 r 1 2 ? r r ? 1 dec saddr 2 4 6 (saddr) (saddr) ? 1 incw rp 1 4 ? rp rp + 1 increment/ decrement decw rp 1 4 ? rp rp ? 1 ror a, 1 1 2 ? (cy, a 7 a 0 , a m ? 1 a m ) 1 time rol a, 1 1 2 ? (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 ? (cy a 0 , a 7 cy, a m ? 1 a m ) 1 time rolc a, 1 1 2 ? (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 a 3 ? 0 (hl) 3 ? 0 , (hl) 7 ? 4 a 3 ? 0 , (hl) 3 ? 0 (hl) 7 ? 4 rotate rol4 [hl] 2 10 12 a 3 ? 0 (hl) 7 ? 4 , (hl) 3 ? 0 a 3 ? 0 , (hl) 7 ? 4 (hl) 3 ? 0 adjba 2 4 ? decimal adjust accumulator after addition bcd adjustment adjbs 2 4 ? decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 ? 7 cy sfr.bit cy, a.bit 2 4 ? cy a.bit cy, psw.bit 3 ? 7 cy psw.bit cy, [hl].bit 2 6 7 cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 ? 8 sfr.bit cy a.bit, cy 2 4 ? a.bit cy psw.bit, cy 3 ? 8 psw.bit cy bit manipulate mov1 [hl].bit, cy 2 6 8 (hl).bit cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 20 instruction set user?s manual u18685ej3v0ud 352 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit and1 cy, [hl].bit 2 6 7 cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit or1 cy, [hl].bit 2 6 7 cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw. bit 3 ? 7 cy cy psw.bit xor1 cy, [hl].bit 2 6 7 cy cy (hl).bit saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 ? 8 sfr.bit 1 a.bit 2 4 ? a.bit 1 psw.bit 2 ? 6 psw.bit 1 set1 [hl].bit 2 6 8 (hl).bit 1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 ? 8 sfr.bit 0 a.bit 2 4 ? a.bit 0 psw.bit 2 ? 6 psw.bit 0 clr1 [hl].bit 2 6 8 (hl).bit 0 set1 cy 1 2 ? cy 1 1 clr1 cy 1 2 ? cy 0 0 bit manipulate not1 cy 1 2 ? cy cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 20 instruction set user?s manual u18685ej3v0ud 353 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy call !addr16 3 7 ? (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callf !addr11 2 5 ? (sp ? 1) (pc + 2) h , (sp ? 2) (pc + 2) l , pc 15 ? 11 00001, pc 10 ? 0 addr11, sp sp ? 2 callt [addr5] 1 6 ? (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (addr5 + 1), pc l (addr5), sp sp ? 2 brk 1 6 ? (sp ? 1) psw, (sp ? 2) (pc + 1) h , (sp ? 3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ? 3, ie 0 ret 1 6 ? pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr call/return retb 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr psw 1 2 ? (sp ? 1) psw, sp sp ? 1 push rp 1 4 ? (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 2 ? psw (sp), sp sp + 1 r r r pop rp 1 4 ? rp h (sp + 1), rp l (sp), sp sp + 2 sp, #word 4 ? 10 sp word sp, ax 2 ? 8 sp ax stack manipulate movw ax, sp 2 ? 8 ax sp !addr16 3 6 ? pc addr16 $addr16 2 6 ? pc pc + 2 + jdisp8 unconditional branch br ax 2 8 ? pch a, pc l x bc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 1 conditional branch bnz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 20 instruction set user?s manual u18685ej3v0ud 354 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 ? 9 pc pc + 3 + jdisp8 if psw.bit = 1 bt [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if psw. bit = 0 bf [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 0 saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit btclr [hl].bit, $addr16 3 10 12 pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b, $addr16 2 6 ? b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 ? c c ? 1, then pc pc + 2 + jdisp8 if c 0 conditional branch dbnz saddr, $addr16 3 8 10 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 sel rbn 2 4 ? rbs1, 0 n nop 1 2 ? no operation ei 2 ? 6 ie 1 (enable interrupt) di 2 ? 6 ie 0 (disable interrupt) halt 2 6 ? set halt mode cpu control stop 2 6 ? set stop mode notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 20 instruction set user?s manual u18685ej3v0ud 355 20.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divuw note except ?r = a? chapter 20 instruction set user?s manual u18685ej3v0ud 356 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand first operand #word ax rp note sfrp saddrp !addr16 sp none ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1 chapter 20 instruction set user?s manual u18685ej3v0ud 357 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop user?s manual u18685ej3v0ud 358 chapter 21 electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd ? 0.5 to +6.5 v supply voltage v ss ? 0.5 to +0.3 v regc pin input voltage v iregc ?0.5 to +3.6 and ?0.5 to v dd v input voltage v i1 p00 to p07, p10 to p17, p20 to p22, p23 note2 , p24 note2 , p25 to p27, p30 to p35 note2 , p120-p123, flmd0 ? 0.3 to v dd + 0.3 note 1 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v per pin ? 40 ma i oh1 total of all pins p00 to p06, p10 to p17, p20 to p22, p23 note2 , p24 note2 , p25 to p27, p30 to p35 note2 , p120 to p122 ? 80 ma output current, high i oh2 per pin rem ? 40 ma per pin 40 ma i ol1 total of all pins p00 to p03, p07, p10 to p17, p20 to p22, p23 note2 , p30 to p35 note2 , p121, p122 150 ma per pin 40 ma output current, low i ol2 total of all pins p04 to p06, p24 note2 , p25 to p27, p120 150 ma operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c notes 1. must be 6.5 v or lower. 2. 38-pin products only. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated valu es at which the product is on the verge of suffering physical damage , and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, t he characteristics of alternate-function pi ns are the same as those of port pins. chapter 21 electrical specifications user?s manual u18685ej3v0ud 359 x1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd 3.6 v, v ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 1.0 4.0 mhz crystal resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 1.0 4.0 mhz note indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the o scillator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. since the cpu is started by the internal high-speed oscillati on clock after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. determine the oscillation stabilizati on time of the ostc register and oscillation stabilization time select regist er (osts) after suffi ciently evaluating the oscillation stabilization time wit h the resonator to be used. internal oscillato r characteristics (t a = ? 40 to +85 c, 1.8 v v dd 3.6 v, v ss = 0 v) resonator parameter conditions min. typ. max. unit 4 mhz internal oscillator internal high-speed oscillation clock frequency (f rh ) note rsts = 1 t a = ? 10 to +70 c 3.92 4.0 4.08 mhz 2.1 v v dd 3.6 v 216 240 276 khz 240 khz internal oscillator internal low-speed oscillation clock frequency (f rl ) 1.8 v v dd < 2.1 v 180 240 300 khz note indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. remark rsts: bit 7 of the internal oscillation mode register (rcm) chapter 21 electrical specifications user?s manual u18685ej3v0ud 360 dc characteristics (1/2) (t a = ? 40 to +85 c, 1.8 v v dd 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit per pin for p00 to p06, p10 to p17, p20 to p22, p23 note2 , p24 note2 , p25 to p27, p30 to p35 note2 , p120 to p122 ?2.0 ma total of all pins p04 to p06, p24 note2 , p25 to p27, p120 ?4.0 ma i oh1 total of all pins p00 to p06, p10 to p17, p20 to p22, p23 note2 , p24 note2 , p25 to p27, p30 to p35 note2 , p121, p122 ?20.0 ma i oh2 p07 (rem) v dd = 3.0 v, v oh2 = 1.0 v ?6.0 ?13.0 ?25.0 ma output current, high note 1 total of all pins note3 ?49.0 ma per pin 1.0 ma i ol1 p00 to p03, p07, p10 to p17, p20 to p22, p23 note2 , p30 to p35 note2 , p121, p122 total 20.0 ma per pin 3.0 ma i ol2 p04 to p06, p24 note2 , p25 to p27, p120 total 30.0 ma output current, low note 4 total of all pins note3 50.0 ma v ih1 p07, p10 to p17, p20 to p22, p23 note2 , p30 to p35 note2 , p121, p122, p123 (kr8) 0.7v dd v dd v v ih2 p00 to p06, p24 note2 , p25 to p27, p120, reset/p123 (intp5) 0.8v dd v dd v input voltage, high v ih3 flmd0 0.9v dd v dd v v il1 p07, p10 to p17, p20 to p22, p23 note2 , p30 to p35 note2 , p121, p122, p123 (kr8) 0 0.3v dd v v il2 p00 to p06, p24 note2 , p25 to p27, p120, reset/p123 (intp5) 0 0.2v dd v input voltage, low v il3 flmd0 0 0.1v dd v v oh1 p00 to p06, p10 to p17, p20 to p22, p23 note2 , p24 note2 , p25 to p27,p30 to p35 note2 , p120 to p122 v dd = 1.8 v i oh1 = ? 1.0 ma v dd ?0.5 v output voltage, high v oh2 p07 v dd = 3.0 v i oh2 = ? 6.0 ma 1.0 v v ol1 p00 to p03, p07, p10 to p17, p20 to p22, p23 note2 , p30 to p35 note2 , p121, p122 v dd = 1.8 v i ol1 = 0.5 ma 0.4 v output voltage, low v ol2 p04 to p06, p24 note2 , p25 to p27, p120 v dd = 2.0 v i ol2 = 1.5 ma 0.1 v notes 1. value of current at which t he device operation is guaranteed even if the cu rrent flows from v dd to an output pin. 2. 38-pin products only. 3. specification under conditions wher e the duty factor is 70% (time fo r which current is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output curr ent of the pins at a duty factor of other than 70% can be calculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7)/(n 0.01) chapter 21 electrical specifications user?s manual u18685ej3v0ud 361 dc characteristics (2/2) (t a = ? 40 to +85 c, 1.8 v v dd 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit i lih1 p00 to p07, p10 to p17, p20 to p22, p23 note1 , p24 note1 , p25 to p27, p30 to p35 note1 , p120, p123 v i = v dd 3 a i/o port mode 3 a input leakage current, high i lih3 p121, p122 (x1, x2) v i = v dd osc mode 20 a i lil1 p00 to p07, p10 to p17, p20 to p22, p23 note1 , p24 note1 , p25 to p27, p30 to p35 note1 , p120, p123 v i = v ss ?3 a i/o port mode ?3 a input leakage current, low i lil2 p121, p122 (x1, x2) v i = v ss osc mode ?20 a r u1 p00 to p07, p20 to p22, p23 note1 , p24 note1 , p25 to p27, p120 to p122 10 20 100 k ? r u2 p10 to p17, p30 to p35 note1 , reset 75 150 300 k ? pull-up resistance r u3 v i = v ss flmd0 1.8 v v dd 3.6 v 10 19.5 52 k ? f xh = 4 mhz note3 , v dd = 3.0 v 0.8 1.2 ma i dd1 operation mode f rh = 4 mhz note4 , v dd = 3.0 v 0.7 1.0 ma f xh = 4 mhz note3 , v dd = 3.0 v 0.25 0.33 ma i dd2 halt mode f rh = 4 mhz note4 , v dd = 3.0 v 0.15 0.28 ma supply current note 2 i dd3 stop mode note4 v dd = 3.0 v 1 20 a watchdog timer operating current i wdt note5 during 240 khz internal low-speed oscillation clock operation 3.2 6.4 a lvi operating current i lvi note6 5.8 12 a notes 1. 38-pin products only. 2. total current flowing into the internal power supply (v dd ), including the peripheral operation current and the input leakage current flowing when the le vel of the input pin is fixed to v dd or v ss . however, the current flowing into the pull-up resistors and the out put current of the port are not included. 3. not including the operating current of the 4 mhz inte rnal oscillator and 240 khz internal oscillator, and the current flowing into the watchdog timer and lvi circuit. 4. not including the operating current of the 240 khz internal oscillator, and the current flowing into the watchdog timer and lvi circuit. 5. current flowing only to the watchdog timer, incl uding the operating current of the 240 khz internal oscillator. the current value of the pd179f11x, 179f12x microcontro ller is the sum of i dd2 or i dd3 and i wdt when the watchdog timer operates in the halt or stop mode. 6. current flowing only to the lvi circuit. the current value of the pd179f11x, 179f12x microcontroller is the sum of i dd2 or i dd3 and i lvi when the lvi circuit operates in the halt or stop mode. chapter 21 electrical specifications user?s manual u18685ej3v0ud 362 remarks 1. f xh : high-speed system clock frequency (x1 clock oscilla tion frequency or external main system clock frequency) 2. f rh : internal high-speed oscillation clock frequency ac characteristics (1) basic operation (t a = ? 40 to +85 c, 1.8 v v dd 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit 2.0 v v dd 3.6 v 0.5 32 s instruction cycle (minimum instruction execution time) t cy main system clock (f xp ) operation 1.8 v v dd < 2.0 v 1 32 s external main system clock frequency f exclk 1.0 4.0 mhz external main system clock input high-level width, low-level width t exclkh, t exclkl (1/f exclk 1/2) ?1 ns 2.1 v v dd 3.6 v 2/f sam + 0.2 note s ti000, ti010 input high-level width, low-level width t tih0 , t til0 1.8 v v dd < 2.1 v 2/f sam + 0.5 note s ti50, ti51 input frequency f ti5 4 mhz ti50, ti51 input high-level width, low-level width t tih5 , t til5 250 ns interrupt input high-level width, low-level width t inth , t intl 1 s key interrupt input low-level width t kr 250 ns reset low-level width t rsl 10 s note selection of f sam = f prs , f prs /4, f prs /256 is possible using bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00). note that when select ing the ti000 valid edge as the count clock, f sam = f prs. chapter 21 electrical specifications user?s manual u18685ej3v0ud 363 t cy vs. v dd (main system clock operation) 5.0 1.0 2.0 0.4 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 3.6 100 0.01 1.8 32 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range 0.5 0.9 ac timing test points v ih v il test points v ih v il external main system clock timing, external subsystem clock timing exclk 0.7v dd (min.) 0.3v dd (max.) 1/f exclk t exclkl t exclkh chapter 21 electrical specifications user?s manual u18685ej3v0ud 364 ti timing ti000, ti010 t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp5 t intl t inth key interrupt input timing t kr kr0 to kr8, kr9 to kr14 note note 38-pin products only reset input timing reset t rsl (2) serial interface (t a = ? 40 to +85 c, 1.8 v v dd 3.6 v, v ss = 0 v) (a) uart6 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbps chapter 21 electrical specifications user?s manual u18685ej3v0ud 365 poc circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v poc 1.7 1.8 1.9 v minimum pulse width t pw 200 s poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pw note internal reset signal by poc circuit will be generated in case t hat the state of v dd < v poc is kept more than 200 s. 200 s is a guaranteed value, so it may generate internal reset signal in case of t pw <200 s. poc detection voltage may become bel ow than operation voltage range (v dd = 1.8 to 3.6v), but cpu does not overrun until po c detection voltage. please notice that it may stop the x1 oscillation before poc reset gener ation, if the oscillator which is not guaranteed its operation in low voltage. chapter 21 electrical specifications user?s manual u18685ej3v0ud 366 lvi circuit characteristics (t a = ? 40 to +85 c, 1.8 v v dd 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit v lvi5 3.37 3.47 3.57 v v lvi6 3.22 3.32 3.42 v v lvi7 3.06 3.16 3.26 v v lvi8 2.91 3.01 3.11 v v lvi9 2.75 2.85 2.95 v v lvi10 2.60 2.70 2.80 v v lvi11 2.45 2.55 2.65 v v lvi12 2.29 2.39 2.49 v v lvi13 2.14 2.24 2.34 v v lvi14 2.00 2.08 2.15 v supply voltage level v lvi15 1.83 1.93 2.03 v detection voltage external input pin note 1 exlvi exlvi < v dd 1.21 v minimum pulse width t lw 200 s operation stabilization wait time note 2 t lwait 10 s notes 1. the exlvi/p120/intp0 pin is used. 2. time required from setting bit 7 (lvion) of the lo w-voltage detection register (lvim) to 1 to operation stabilization remark v lvi(n ? 1) > v lvin : n = 6 to 15 lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t lwait lvion 1 chapter 21 electrical specifications user?s manual u18685ej3v0ud 367 data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.3 3.6 v v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode detection voltage for data memory retention at battery exchange and power supply decrease (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit detection voltage for ram retention v ld lvdet0 bit ?1? ?0? 1.30 1.40 1.50 v flash memory programming characteristics (t a = ? 40 to +85 c, 2.0 v v dd 3.6 v, v ss = 0 v) ? basic characteristics parameter symbol conditions min. typ. max. unit v dd supply current i dd f xp = 4 mhz (typ.) 4.5 11.0 ma all block t eraca 20 200 ms erase time note 1, 2 block unit t erasa 20 200 ms write time (in 8-bit units) note 1 t wrwa 10 100 s number of rewrites per chip c erwr 1 erase + 1 write after erase = 1 rewrite note 3 1000 times notes 1. characteristic of the flash memory. 2. the prewrite time before eras ure and the erase verify time (writeback time) are not included. 3. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. remark f xp : main system clock oscillation frequency chapter 21 electrical specifications user?s manual u18685ej3v0ud 368 ? serial write operation characteristics parameter symbol conditions min. typ. max. unit count start time from reset to flmd0 t rfcf 4.1 17.1 ms count execution time t count 10.8 13.2 ms flmd0 counter high level width / low level width t ch / t cl t c 0.45 s flmd0 counter rise time / fall time t r / t f 12.5 s reset flmd0 v dd 0 v v dd 0 v t rfcf t cl t f t r t count t ch t c user?s manual u18685ej3v0ud 369 chapter 22 package drawings ? pd179f110mc-cab-ax, 179f111mc-cab-ax , 179f112mc-cab-ax, 179f113mc-cab-ax, 179f114mc-cab-ax 16 30 1 m s s v 30-pin plastic ssop (7.62mm (300)) detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item dimensions a b c e f g h i j l m n d 0.30 0.65 (t.p.) 0.10 0.05 1.30 0.10 1.20 8.10 0.20 6.10 0.10 1.00 0.20 0.50 0.13 0.10 0.22 + 0.10 ? 0.05 k 0.15 + 0.05 ? 0.01 p 3 + 5 ? 3 (unit:mm) p30mc-65-cab v w w a i f g e c n d m b k h j p u t l 9.70 0.10 t u v 0.25(t.p.) 0.60 0.15 0.25 max. w 0.15 max. 15 chapter 22 package drawings user?s manual u18685ej3v0ud 370 ? pd179f122mc-gaa-ax, 179f123m c-gaa-ax, 179f124mc-gaa-ax 20 38 1 m s s v 38-pin plastic ssop (7.62mm (300)) detail of lead end note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item dimensions a b c e f g h i j l m n d 0.30 0.65 (t.p.) 0.125 0.075 2.00 max. 1.70 0.10 8.10 0.20 6.10 0.10 1.00 0.20 0.50 0.10 0.10 0.30 + 0.10 ? 0.05 k 0.15 + 0.10 ? 0.05 p 3 + 5 ? 3 (unit:mm) p38mc-65-gaa v w w a i f g e c n d m b k h j p u t l 12.30 0.10 t u v 0.25(t.p.) 0.60 0.15 0.25 max. w 0.15 max. 19 user?s manual u18685ej3v0ud 371 appendix a development tools the following devel opment tools are available for the deve lopment of systems that employ the pd179f11x, 179f12x microcontrollers. figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, pr oducts supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computer s, refer to the explanation for ibm pc/at compatibles. ? windows tm unless otherwise specified, ?windows? means the following oss. ? windows 98 ? windows nt tm ? windows 2000 ? windows xp appendix a development tools user?s manual u18685ej3v0ud 372 figure a-1. development tool configuration (1/2) (1) when using the in-circuit emulator qb-179f124 language processing software ? assembler package ? c compiler package ? device file note 1 ? c library source file note 2 debugging software ? integrated debugger note 4 host machine (pc or ews) qb179f124 note 4 emulation probe target system flash memory programmer flash memory write adapter flash memory ? software package ? project manager software package flash memory write environment control software (windows only) note 3 power supply unit note 4 usb interface cable note 4 notes 1. download the device file (df179124) for the pd179f11x, 179f12x microcontrollers from the download site for development tools (http ://www.necel.com/micro/ods/eng/index.html). 2. the c library source file is not included in the software package. 3. the project manager pm+ is in cluded in the assembler package. the pm+ is only used for windows. 4. the qb-179f124 is supplied with the integrated debugger id78k0-qb, a usb interface cable, a power supply unit, the on-chip debug emulator qb-mini2, c onnection cables (10-pin and 16-pin cables), and the 78k0-ocd board. any other pr oducts are sold separately. download the software for operating the qb-mini2 from the download site for development tools (http://www.necel.com/micro/ods/eng/ind ex.html) when using the qb-mini2. appendix a development tools user?s manual u18685ej3v0ud 373 figure a-1. development tool configuration (2/2) (2) when using the on-chip debug emulat or with programming function qb-mini2 qb-mini2 note 4 qb-mini2 note 4 78k0-ocd board note 4 language processing software ? assembler package ? c compiler package ? device file note 1 ? c library source file note 2 debugging software ? integrated debugger note 1 host machine (pc or ews) usb interface cable note 4 connection cable (10-pin/16-pin cable) note 4 target connector target system connection cable (16-pin cable) note 4 ? software package ? project manager software package appendix a development tools user?s manual u18685ej3v0ud 374 a.1 software package development tools (software) common to the 78k0 microcontrollers and pd179f11x, 179f12x microcontrollers are combined in this package. sp78k0 78k0 microcontroller software package part number: s sp78k0 remark in the part number differs depending on the host machine and os used. s sp78k0 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functi ons capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combi nation with a device file (df179124) (sold separately). appendix a development tools user?s manual u18685ej3v0ud 375 remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 s cc78k0-l host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4) solaris tm (rel. 2.5.1) cd-rom s df179124 host machine os supply medium ab13 windows (japanese version) bb13 pc-9800 series, ibm pc/at compatibles windows (english version) 3.5-inch 2hd fd a.3 control software pm+ project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. appendix a development tools user?s manual u18685ej3v0ud 376 a.4 flash memory writing tools a.4.1 when using flash memory program mer pg-fp4, fl-pr4, pg-fp5 and fl-pr5 pg-fp4, fl-pr4, pg-fp5, fl-pr5 flash memory programmer flash memory programmer dedica ted to microcontrollers with on-chip flash memory. fa-179f114mc-cab-mx fa-179f124mc-gaa-mx flash memory writing adapter flash memory writing adapter used conne cted to the flash memory programmer. ? fa-179f114mc-cab-mx: for 30-pin plastic ssop (mc-cab type) ? fa-179f124mc-gaa-mx: for 38-pin plastic ssop (mc-gaa type) remarks 1. fl-pr4, fl-pr5, fa-179f114mc-cab-mx, and fa-1 79f124mc-gaa-mx are products of naito densei machida mfg. co., ltd. tel: +81-42-750-4172 naito densei machida mfg. co., ltd. 2. use the latest version of the flash memory programming adapter. a.4.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this is a flash memory programmer dedicat ed to microcontrollers with on-chip flash memory. it is available also as on-chip debug emulator which serves to debug hardware and software when developing application systems using the pd179f11x, 179f12x microcontrollers. when using th is as flash memory program mer, it should be used in combination with a connection cable (16-pin cable) and a usb interface cable that is used to connect the host machine. target connector specific ations 16-pin general-purpose connector (2.54 mm pitch) remarks 1. the qb-mini2 is supplied with a usb interface cable, connection cables (10-pin and 16-pin cables), and the 78k0-ocd board. the connection cable (1 0-pin cable) and the 78k0-ocd board are used only when using the on-chip debug function. 2. download the software for operating the qb-mini2 from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). appendix a development tools user?s manual u18685ej3v0ud 377 a.5 debugging tools (hardware) a.5.1 when using in-cir cuit emulator qb-179f124 qb-179f124 in-circuit emulator this in-circuit emulator serves to debug har dware and software when developing application systems using the pd179f11x, 179f12x microcontrollers. it supports to the integrated debugger (id78k0-qb). this emulator should be used in combination with a power supply unit and emulation probe, and the usb is used to conn ect this emulator to the host machine. qb-144-ca-01 check pin adapter this check pin adapter is used in waveform monitoring using the oscilloscope, etc. qb-80-ep-01t emulation probe this emulation probe is flexible type and used to connect the in-circuit emulator and target system. qb-30mc-ea-02t, qb-38mc-ea-02t exchange adapter this exchange adapter is used to perform pin conver sion from the in-circuit emulator to target connector. ? qb-30mc-ea-02t: for 30-pin plastic ssop (mc-cab type) ? qb-38mc-ea-02t: for 38-pin plastic ssop (mc-gaa type) qb-30mc-ys-01t, qb-38mc-ys-01t space adapter this space adapter is used to adjust the height bet ween the target system and in-circuit emulator. ? qb-30mc-ys-01t: for 30-pin plastic ssop (mc-cab type) ? qb-38mc-ys-01t: for 38-pin plastic ssop (mc-gaa type) qb-30mc-yq-01t, qb-38mc-yq-01t yq connector this yq connector is used to connect the target connector and exchange adapter. ? qb-30mc-yq-01t: for 30-pin plastic ssop (mc-cab type) ? qb-38mc-yq-01t: for 38-pin plastic ssop (mc-gaa type) qb-30mc-hq-01t, qb-38mc-hq-01t mount adapter this mount adapter is used to mount the target device with socket. ? qb-30mc-hq-01t: for 30-pin plastic ssop (mc-cab type) ? qb-38mc-hq-01t: for 38-pin plastic ssop (mc-gaa type) qb-30mc-nq-01t, qb-38mc-nq-01t target connector this target connector is used to mount on the target system. ? qb-30mc-nq-01t: for 30-pin plastic ssop (mc-cab type) ? qb-38mc-nq-01t: for 38-pin plastic ssop (mc-gaa type) remarks 1. the qb-179f124 is supplied wit h the integrated debugger id78k0- qb, a usb interface cable, a power supply unit, the on-chip debug emulator qb-mini2, connection cables (10-pin and 16-pin cables), and the 78k0-ocd board. download the software for operating the qb-mini 2 from the download site for development tools (http://www.necel.com/micro/ods/eng/ind ex.html) when using the qb-mini2. 2. the packed contents differ depending on the part number, as follows. packed contents part number in-circuit emulator emulation probe exch ange adapter yq connector target connector qb-179f124-zzz none qb-179f124-t30mc qb-30mc-ea-02t qb-30mc-yq-01t qb-30mc-nq-01t qb-179f124-t38mc qb-179f124 qb-80-ep-01t qb-38mc-ea-02t qb-38mc-yq-01t qb-38mc-nq-01t appendix a development tools user?s manual u18685ej3v0ud 378 a.5.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this on-chip debug emulator serves to debug hardware and software when developing application systems using the pd179f11x, 179f12x microcontrollers. it is available also as flash memory programmer dedicated to microcontrollers wi th on-chip flash memory. when using this as on-chip debug emulator, it should be used in comb ination with a connection cable (10-pin cable or 16-pin cable), a usb interface cable that is us ed to connect the host machine, and the 78k0-ocd board. target connector specifications 10-pin general-purpose connector (2. 54 mm pitch) or 16-pin general-purpose connector (2.54 mm pitch) remarks 1. the qb-mini2 is supplied with a usb interface cable, connection cables (10-pin and 16-pin cables), and the 78k0-ocd board. the connection cable (1 0-pin cable) and the 78k0-ocd board are used only when using the on-chip debug function. 2. download the software for operating the qb-mini2 from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). a.6 debugging tools (software) this debugger supports the in-circuit emul ators for the 78k0 microcontrollers and pd179f11x, 179f12x microcontrollers. t he id78k0-qb is a windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory di splay with the trace result. it should be used in combination with the device file (sold separately). id78k0-qb integrated debugger part number: s id78k0-qb remark in the part number differs depending on the host machine and os used. s id78k0-qb host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom user?s manual u18685ej3v0ud 379 appendix b revision history b.1 major revisions in this edition (1/2) page description chapter 1 outline p. 16 modification of 1.3 ordering information p. 20 modification of internal low-speed oscillation clock (for wdt) in 1.8 outline of functions chapter 2 pin functions p. 28 modification of table 2-1. pin i/o circuit types chapter 3 cpu architecture p. 55 modification of 3.3.3 table indirect addressing chapter 4 port fuctions p. 68 modification of figure 4-2. block diagram of p00 and p03 p. 83 modification of 4.3 (3) pull-up resistor option registers (pu0 to pu2, pu3, and pu12) p. 86 modification of 4.5 settings of port mode register, output latch, pull-up resistor option register, and port output mode register when using alternate function chapter 5 clock generator p. 88 modification of (2) internal low-speed oscillation clock (clock for watchdog timer) in 5.1 functions of clock generator . p. 90 modification of figure 5-1. block diagram of clock generator p. 92 deletion of caution 1 from figure 5-2. format of clock operation mode select register (oscctl) p. 99 addition of caution to figure 5-9. example of external circuit of x1 oscillator p. 101 modification of 5.4.3 internal low-speed oscillator p. 107 addition of 5.6.3 example of controlling internal low-speed oscillation clock p. 111 addition of caution to table 5-4. cpu clock transition and sfr register setting examples (2/2) chapter 8 8-bit timers h0 and h1 p. 205 modification of figure 8-6. format of 8-bit timer h mode register 1 (tmhmd1) chapter 9 watchdog timer p. 228 modification of 9.4.1 controlling operation of watchdog timer in caution 5 p. 228 modification of table 9-3. setting of overflow time of watchdog timer (when 2.1 v v dd 3.6 v) p. 229 addition of table 9-4. setting of overflow time of watchdog timer (when 1.8 v v dd < 2.1 v) p. 230 modification of caution and remark of table 9-5. setting window open period of watchdog timer chapter 13 standby function p. 283 deletion of caution 1 from 13.1.1 standby function p. 284 modification of figure 13-1. format of oscillation stabilization time counter status register (ostc) p. 285 modification of figure 13-2. format of oscillation stabilization time select register (osts) p. 290 addition of caution 4 to table 13-3. operating statuses in stop mode chapter 17 option byte p. 324 modification of figure 17-1. format of option byte (1/2) appendix b revision history user?s manual u18685ej3v0ud 380 (2/2) page description chapter 18 flash memory p. 327 modification of note of table 18-2. example of wiring between pd179f11x microcontroller and dedicated flash memory programmer p. 328 modification of remark of figure 18-2. example of wiring adapter for flash memory writing (30-pin products) p. 329 modification of figure 18-3. environment for writing program to flash memory p. 329 modification of figure 18-4. communication with dedicated flash memory programmer p. 330 modification of note of table 18-3. pin connection p. 333 modification of 18.5.6 other signal pins p. 334 modification of figure 18-9. flash memory manipulation procedure p. 335 modification of figure 18-11. communication commands p. 336 modification of table 18-7. flash memory control commands p. 337 modification of 18.7 security settings p. 337 modification of table 18-9. relationship between enabling security function and command p. 338 modification of table 18-10. setting security in each programming mode chapter 20 instruction set p. 353 modification of 20.2 operation list chapter 21 electrical specifications p. 367 modification of flash memory programming characteristics (t a = ? 40 to +85c, 2.0 v v dd 3.6 v, v ss = 0 v) appendix a development tools p. 376 modification of a.4.1 when using flash memory programmer pg-fp4, fl-pr4, pg-fp5 and fl-pr5 appendix b revision history p. 380 addition of b.2 revision history up to previous editions appendix b revision history user?s manual u18685ej3v0ud 381 b.2 revision history up to previous editions here is the revision history of the preceding editi ons. chapter indicates the chapter of each edition. edition description applied to: addition of description to 2.2.5 p120 to p123 (port 12) chapter 2 pin functions modification of table 3-6. special function register list chapter 3 cpu architecture modification of table 4-2. port configuration modification of figure 4-14. block diagram of p123 addition of description to 4.3 registers controlling port function modification of figure 4-17. format of pull-up resistor option register addition of 4.3 (5) reset pin mode register (rstmask) chapter 4 port fuctions addition of description to 12.1 functions of key interrupt chapter 12 key interrupt function modification of table 14-2. hardware statuses after reset acknowledgment chapter 14 reset functions addition of description to 16.1 functions of low-voltage detector addition of 16.6 ram data retention detector chapter 16 low- voltage detector modification of table 18-7. flash memory control commands modification of 18.7 security settings addition of 18.8 flash memory programming by self-programming chapter 18 flash memory modification of figure 19-1. connection example of qb-mini2 and pd179f11x, 179f12x microcontrollers (when ocd0a/x1 and ocd0b/x2 are used) modification of figure 19-2. connection example of qb-mini2 and pd179f11x, 179f12x microcontroller (when ocd1a/p04 and ocd1b/p05 are used) chapter 19 on-chip debug function 2nd edition modification of chapter 21 electrical specifications chapter 21 electrical specifications nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010-8235-1155 http://www.cn.necel.com/ shanghai branch room 2509-2510, bank of china tower, 200 yincheng road central, pudong new area, shanghai, p.r.china p.c:200120 tel:021-5888-5400 http://www.cn.necel.com/ shenzhen branch unit 01, 39/f, excellence times square building, no. 4068 yi tian road, futian district, shenzhen, p.r.china p.c:518048 tel:0755-8282-9800 http://www.cn.necel.com/ nec electronics hong kong ltd. unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: 2886-9318 http://www.hk.necel.com/ nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-8175-9600 http://www.tw.necel.com/ nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ nec electronics korea ltd. 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 http://www.kr.necel.com/ for further information, please contact: g0706 [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http://www.eu.necel.com/ hanover office podbielskistrasse 166 b 30177 hannover tel: 0 511 33 40 2-0 munich office werner-eckert-strasse 9 81829 mnchen tel: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart tel: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay cdex france tel: 01-3067-5800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands steijgerweg 6 5616 hs eindhoven the netherlands tel: 040 265 40 10 |
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